diff options
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/c-r4k.c | 78 | ||||
-rw-r--r-- | arch/mips/mm/init.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/pg-r4k.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/tlbex.c | 2 |
4 files changed, 73 insertions, 10 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4182e1176fae..4a43924cd4fc 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -29,6 +29,27 @@ | |||
29 | #include <asm/war.h> | 29 | #include <asm/war.h> |
30 | #include <asm/cacheflush.h> /* for run_uncached() */ | 30 | #include <asm/cacheflush.h> /* for run_uncached() */ |
31 | 31 | ||
32 | |||
33 | /* | ||
34 | * Special Variant of smp_call_function for use by cache functions: | ||
35 | * | ||
36 | * o No return value | ||
37 | * o collapses to normal function call on UP kernels | ||
38 | * o collapses to normal function call on systems with a single shared | ||
39 | * primary cache. | ||
40 | */ | ||
41 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, | ||
42 | int retry, int wait) | ||
43 | { | ||
44 | preempt_disable(); | ||
45 | |||
46 | #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) | ||
47 | smp_call_function(func, info, retry, wait); | ||
48 | #endif | ||
49 | func(info); | ||
50 | preempt_enable(); | ||
51 | } | ||
52 | |||
32 | /* | 53 | /* |
33 | * Must die. | 54 | * Must die. |
34 | */ | 55 | */ |
@@ -299,7 +320,7 @@ static void r4k_flush_cache_all(void) | |||
299 | if (!cpu_has_dc_aliases) | 320 | if (!cpu_has_dc_aliases) |
300 | return; | 321 | return; |
301 | 322 | ||
302 | on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); | 323 | r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); |
303 | } | 324 | } |
304 | 325 | ||
305 | static inline void local_r4k___flush_cache_all(void * args) | 326 | static inline void local_r4k___flush_cache_all(void * args) |
@@ -314,13 +335,14 @@ static inline void local_r4k___flush_cache_all(void * args) | |||
314 | case CPU_R4400MC: | 335 | case CPU_R4400MC: |
315 | case CPU_R10000: | 336 | case CPU_R10000: |
316 | case CPU_R12000: | 337 | case CPU_R12000: |
338 | case CPU_R14000: | ||
317 | r4k_blast_scache(); | 339 | r4k_blast_scache(); |
318 | } | 340 | } |
319 | } | 341 | } |
320 | 342 | ||
321 | static void r4k___flush_cache_all(void) | 343 | static void r4k___flush_cache_all(void) |
322 | { | 344 | { |
323 | on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); | 345 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); |
324 | } | 346 | } |
325 | 347 | ||
326 | static inline void local_r4k_flush_cache_range(void * args) | 348 | static inline void local_r4k_flush_cache_range(void * args) |
@@ -341,7 +363,7 @@ static inline void local_r4k_flush_cache_range(void * args) | |||
341 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | 363 | static void r4k_flush_cache_range(struct vm_area_struct *vma, |
342 | unsigned long start, unsigned long end) | 364 | unsigned long start, unsigned long end) |
343 | { | 365 | { |
344 | on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); | 366 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); |
345 | } | 367 | } |
346 | 368 | ||
347 | static inline void local_r4k_flush_cache_mm(void * args) | 369 | static inline void local_r4k_flush_cache_mm(void * args) |
@@ -370,7 +392,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm) | |||
370 | if (!cpu_has_dc_aliases) | 392 | if (!cpu_has_dc_aliases) |
371 | return; | 393 | return; |
372 | 394 | ||
373 | on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); | 395 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); |
374 | } | 396 | } |
375 | 397 | ||
376 | struct flush_cache_page_args { | 398 | struct flush_cache_page_args { |
@@ -461,7 +483,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma, | |||
461 | args.addr = addr; | 483 | args.addr = addr; |
462 | args.pfn = pfn; | 484 | args.pfn = pfn; |
463 | 485 | ||
464 | on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); | 486 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); |
465 | } | 487 | } |
466 | 488 | ||
467 | static inline void local_r4k_flush_data_cache_page(void * addr) | 489 | static inline void local_r4k_flush_data_cache_page(void * addr) |
@@ -471,7 +493,7 @@ static inline void local_r4k_flush_data_cache_page(void * addr) | |||
471 | 493 | ||
472 | static void r4k_flush_data_cache_page(unsigned long addr) | 494 | static void r4k_flush_data_cache_page(unsigned long addr) |
473 | { | 495 | { |
474 | on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); | 496 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); |
475 | } | 497 | } |
476 | 498 | ||
477 | struct flush_icache_range_args { | 499 | struct flush_icache_range_args { |
@@ -514,7 +536,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) | |||
514 | args.start = start; | 536 | args.start = start; |
515 | args.end = end; | 537 | args.end = end; |
516 | 538 | ||
517 | on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); | 539 | r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); |
518 | instruction_hazard(); | 540 | instruction_hazard(); |
519 | } | 541 | } |
520 | 542 | ||
@@ -590,7 +612,7 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma, | |||
590 | args.vma = vma; | 612 | args.vma = vma; |
591 | args.page = page; | 613 | args.page = page; |
592 | 614 | ||
593 | on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); | 615 | r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); |
594 | } | 616 | } |
595 | 617 | ||
596 | 618 | ||
@@ -689,7 +711,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) | |||
689 | 711 | ||
690 | static void r4k_flush_cache_sigtramp(unsigned long addr) | 712 | static void r4k_flush_cache_sigtramp(unsigned long addr) |
691 | { | 713 | { |
692 | on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); | 714 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); |
693 | } | 715 | } |
694 | 716 | ||
695 | static void r4k_flush_icache_all(void) | 717 | static void r4k_flush_icache_all(void) |
@@ -812,6 +834,7 @@ static void __init probe_pcache(void) | |||
812 | 834 | ||
813 | case CPU_R10000: | 835 | case CPU_R10000: |
814 | case CPU_R12000: | 836 | case CPU_R12000: |
837 | case CPU_R14000: | ||
815 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); | 838 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
816 | c->icache.linesz = 64; | 839 | c->icache.linesz = 64; |
817 | c->icache.ways = 2; | 840 | c->icache.ways = 2; |
@@ -965,9 +988,11 @@ static void __init probe_pcache(void) | |||
965 | c->dcache.flags |= MIPS_CACHE_PINDEX; | 988 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
966 | case CPU_R10000: | 989 | case CPU_R10000: |
967 | case CPU_R12000: | 990 | case CPU_R12000: |
991 | case CPU_R14000: | ||
968 | case CPU_SB1: | 992 | case CPU_SB1: |
969 | break; | 993 | break; |
970 | case CPU_24K: | 994 | case CPU_24K: |
995 | case CPU_34K: | ||
971 | if (!(read_c0_config7() & (1 << 16))) | 996 | if (!(read_c0_config7() & (1 << 16))) |
972 | default: | 997 | default: |
973 | if (c->dcache.waysize > PAGE_SIZE) | 998 | if (c->dcache.waysize > PAGE_SIZE) |
@@ -1091,6 +1116,7 @@ static void __init setup_scache(void) | |||
1091 | 1116 | ||
1092 | case CPU_R10000: | 1117 | case CPU_R10000: |
1093 | case CPU_R12000: | 1118 | case CPU_R12000: |
1119 | case CPU_R14000: | ||
1094 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); | 1120 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1095 | c->scache.linesz = 64 << ((config >> 13) & 1); | 1121 | c->scache.linesz = 64 << ((config >> 13) & 1); |
1096 | c->scache.ways = 2; | 1122 | c->scache.ways = 2; |
@@ -1135,6 +1161,31 @@ static void __init setup_scache(void) | |||
1135 | c->options |= MIPS_CPU_SUBSET_CACHES; | 1161 | c->options |= MIPS_CPU_SUBSET_CACHES; |
1136 | } | 1162 | } |
1137 | 1163 | ||
1164 | void au1x00_fixup_config_od(void) | ||
1165 | { | ||
1166 | /* | ||
1167 | * c0_config.od (bit 19) was write only (and read as 0) | ||
1168 | * on the early revisions of Alchemy SOCs. It disables the bus | ||
1169 | * transaction overlapping and needs to be set to fix various errata. | ||
1170 | */ | ||
1171 | switch (read_c0_prid()) { | ||
1172 | case 0x00030100: /* Au1000 DA */ | ||
1173 | case 0x00030201: /* Au1000 HA */ | ||
1174 | case 0x00030202: /* Au1000 HB */ | ||
1175 | case 0x01030200: /* Au1500 AB */ | ||
1176 | /* | ||
1177 | * Au1100 errata actually keeps silence about this bit, so we set it | ||
1178 | * just in case for those revisions that require it to be set according | ||
1179 | * to arch/mips/au1000/common/cputable.c | ||
1180 | */ | ||
1181 | case 0x02030200: /* Au1100 AB */ | ||
1182 | case 0x02030201: /* Au1100 BA */ | ||
1183 | case 0x02030202: /* Au1100 BC */ | ||
1184 | set_c0_config(1 << 19); | ||
1185 | break; | ||
1186 | } | ||
1187 | } | ||
1188 | |||
1138 | static inline void coherency_setup(void) | 1189 | static inline void coherency_setup(void) |
1139 | { | 1190 | { |
1140 | change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); | 1191 | change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); |
@@ -1155,6 +1206,15 @@ static inline void coherency_setup(void) | |||
1155 | case CPU_R4400MC: | 1206 | case CPU_R4400MC: |
1156 | clear_c0_config(CONF_CU); | 1207 | clear_c0_config(CONF_CU); |
1157 | break; | 1208 | break; |
1209 | /* | ||
1210 | * We need to catch the ealry Alchemy SOCs with | ||
1211 | * the write-only co_config.od bit and set it back to one... | ||
1212 | */ | ||
1213 | case CPU_AU1000: /* rev. DA, HA, HB */ | ||
1214 | case CPU_AU1100: /* rev. AB, BA, BC ?? */ | ||
1215 | case CPU_AU1500: /* rev. AB */ | ||
1216 | au1x00_fixup_config_od(); | ||
1217 | break; | ||
1158 | } | 1218 | } |
1159 | } | 1219 | } |
1160 | 1220 | ||
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index c22308b93ff0..33f6e1cdfd5b 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c | |||
@@ -227,7 +227,7 @@ void __init mem_init(void) | |||
227 | for (tmp = 0; tmp < max_low_pfn; tmp++) | 227 | for (tmp = 0; tmp < max_low_pfn; tmp++) |
228 | if (page_is_ram(tmp)) { | 228 | if (page_is_ram(tmp)) { |
229 | ram++; | 229 | ram++; |
230 | if (PageReserved(mem_map+tmp)) | 230 | if (PageReserved(pfn_to_page(tmp))) |
231 | reservedpages++; | 231 | reservedpages++; |
232 | } | 232 | } |
233 | 233 | ||
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index e4390dc3eb48..b7c749232ffe 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c | |||
@@ -357,6 +357,7 @@ void __init build_clear_page(void) | |||
357 | 357 | ||
358 | case CPU_R10000: | 358 | case CPU_R10000: |
359 | case CPU_R12000: | 359 | case CPU_R12000: |
360 | case CPU_R14000: | ||
360 | pref_src_mode = Pref_LoadStreamed; | 361 | pref_src_mode = Pref_LoadStreamed; |
361 | pref_dst_mode = Pref_StoreStreamed; | 362 | pref_dst_mode = Pref_StoreStreamed; |
362 | break; | 363 | break; |
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 053dbacac56b..54507be2ab5b 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -875,6 +875,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, | |||
875 | 875 | ||
876 | case CPU_R10000: | 876 | case CPU_R10000: |
877 | case CPU_R12000: | 877 | case CPU_R12000: |
878 | case CPU_R14000: | ||
878 | case CPU_4KC: | 879 | case CPU_4KC: |
879 | case CPU_SB1: | 880 | case CPU_SB1: |
880 | case CPU_SB1A: | 881 | case CPU_SB1A: |
@@ -906,6 +907,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, | |||
906 | case CPU_4KEC: | 907 | case CPU_4KEC: |
907 | case CPU_24K: | 908 | case CPU_24K: |
908 | case CPU_34K: | 909 | case CPU_34K: |
910 | case CPU_74K: | ||
909 | i_ehb(p); | 911 | i_ehb(p); |
910 | tlbw(p); | 912 | tlbw(p); |
911 | break; | 913 | break; |