6 files changed, 32 insertions, 8 deletions

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index a0bcdbb81d41..729e7702b1de 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -224,6 +224,20 @@ static void probe_octeon(void)
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
 
+        case CPU_CAVIUM_OCTEON3:
+                c->icache.linesz = 128;
+                c->icache.sets = 16;
+                c->icache.ways = 39;
+                c->icache.flags |= MIPS_CACHE_VTAG;
+                icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+                c->dcache.linesz = 128;
+                c->dcache.ways = 32;
+                c->dcache.sets = 8;
+                dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+                c->options |= MIPS_CPU_PREFETCH;
+                break;
+
         default:
                 panic("Unsupported Cavium Networks CPU type");
                 break;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index aaccf1c10699..664e523653d0 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -50,16 +50,20 @@ static inline struct page *dma_addr_to_page(struct device *dev,
 }
 
 /*
+ * The affected CPUs below in 'cpu_needs_post_dma_flush()' can
+ * speculatively fill random cachelines with stale data at any time,
+ * requiring an extra flush post-DMA.
+ *
  * Warning on the terminology - Linux calls an uncached area coherent;
  * MIPS terminology calls memory areas with hardware maintained coherency
  * coherent.
  */
-
-static inline int cpu_is_noncoherent_r10000(struct device *dev)
+static inline int cpu_needs_post_dma_flush(struct device *dev)
 {
         return !plat_device_is_coherent(dev) &&
-               (current_cpu_type() == CPU_R10000 ||
-               current_cpu_type() == CPU_R12000);
+               (boot_cpu_type() == CPU_R10000 ||
+                boot_cpu_type() == CPU_R12000 ||
+                boot_cpu_type() == CPU_BMIPS5000);
 }
 
 static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
@@ -230,7 +234,7 @@ static inline void __dma_sync(struct page *page,
 static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
         size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
 {
-        if (cpu_is_noncoherent_r10000(dev))
+        if (cpu_needs_post_dma_flush(dev))
                 __dma_sync(dma_addr_to_page(dev, dma_addr),
                            dma_addr & ~PAGE_MASK, size, direction);
 
@@ -284,7 +288,7 @@ static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 static void mips_dma_sync_single_for_cpu(struct device *dev,
         dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
 {
-        if (cpu_is_noncoherent_r10000(dev))
+        if (cpu_needs_post_dma_flush(dev))
                 __dma_sync(dma_addr_to_page(dev, dma_handle),
                            dma_handle & ~PAGE_MASK, size, direction);
 }
@@ -305,7 +309,7 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev,
 
         /* Make sure that gcc doesn't leave the empty loop body.  */
         for (i = 0; i < nelems; i++, sg++) {
-                if (cpu_is_noncoherent_r10000(dev))
+                if (cpu_needs_post_dma_flush(dev))
                         __dma_sync(sg_page(sg), sg->offset, sg->length,
                                    direction);
         }
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index d4ea5c9c4a93..06ce17c2a905 100644
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -12,6 +12,7 @@
 #include <linux/swap.h>
 #include <linux/hugetlb.h>
 
+#include <asm/cpu-features.h>
 #include <asm/pgtable.h>
 
 static inline pte_t gup_get_pte(pte_t *ptep)
@@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
         len = (unsigned long) nr_pages << PAGE_SHIFT;
 
         end = start + len;
-        if (end < start)
+        if (end < start || cpu_has_dc_aliases)
                 goto slow_irqon;
 
         /* XXX: batch / limit 'nr' */
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4e73f10a7519..e205ef598e97 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -254,6 +254,7 @@ void copy_from_user_page(struct vm_area_struct *vma,
                         SetPageDcacheDirty(page);
         }
 }
+EXPORT_SYMBOL_GPL(copy_from_user_page);
 
 void __init fixrange_init(unsigned long start, unsigned long end,
         pgd_t *pgd_base)
diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S
index 30a494db99c2..79bca3130bd1 100644
--- a/arch/mips/mm/tlb-funcs.S
+++ b/arch/mips/mm/tlb-funcs.S
@@ -16,10 +16,12 @@
 
 #define FASTPATH_SIZE   128
 
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
 LEAF(tlbmiss_handler_setup_pgd)
         .space          16 * 4
 END(tlbmiss_handler_setup_pgd)
 EXPORT(tlbmiss_handler_setup_pgd_end)
+#endif
 
 LEAF(handle_tlbm)
         .space          FASTPATH_SIZE * 4
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 556cb4815770..821b45175dc1 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -85,6 +85,7 @@ static int use_bbit_insns(void)
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
         case CPU_CAVIUM_OCTEON2:
+        case CPU_CAVIUM_OCTEON3:
                 return 1;
         default:
                 return 0;
@@ -95,6 +96,7 @@ static int use_lwx_insns(void)
 {
         switch (current_cpu_type()) {
         case CPU_CAVIUM_OCTEON2:
+        case CPU_CAVIUM_OCTEON3:
                 return 1;
         default:
                 return 0;