4 files changed, 46 insertions, 43 deletions

diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 76935e320214..27a5b466c85c 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -26,7 +26,7 @@
 static unsigned long icache_size, dcache_size;          /* Size in bytes */
 static unsigned long icache_lsize, dcache_lsize;        /* Size in bytes */
 
-unsigned long __init r3k_cache_size(unsigned long ca_flags)
+unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags)
 {
         unsigned long flags, status, dummy, size;
         volatile unsigned long *p;
@@ -61,7 +61,7 @@ unsigned long __init r3k_cache_size(unsigned long ca_flags)
         return size * sizeof(*p);
 }
 
-unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
+unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags)
 {
         unsigned long flags, status, lsize, i;
         volatile unsigned long *p;
@@ -90,7 +90,7 @@ unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
         return lsize * sizeof(*p);
 }
 
-static void __init r3k_probe_cache(void)
+static void __cpuinit r3k_probe_cache(void)
 {
         dcache_size = r3k_cache_size(ST0_ISC);
         if (dcache_size)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 27096751ddce..71df3390c07b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -43,12 +43,12 @@
  *    primary cache.
  */
 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
-                                   int retry, int wait)
+                                   int wait)
 {
         preempt_disable();
 
 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
-        smp_call_function(func, info, retry, wait);
+        smp_call_function(func, info, wait);
 #endif
         func(info);
         preempt_enable();
@@ -350,7 +350,7 @@ static inline void local_r4k___flush_cache_all(void * args)
 
 static void r4k___flush_cache_all(void)
 {
-        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
+        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
 }
 
 static inline int has_valid_asid(const struct mm_struct *mm)
@@ -397,7 +397,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
         int exec = vma->vm_flags & VM_EXEC;
 
         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
-                r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+                r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
 }
 
 static inline void local_r4k_flush_cache_mm(void * args)
@@ -429,7 +429,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
         if (!cpu_has_dc_aliases)
                 return;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
 }
 
 struct flush_cache_page_args {
@@ -521,7 +521,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
         args.addr = addr;
         args.pfn = pfn;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
 }
 
 static inline void local_r4k_flush_data_cache_page(void * addr)
@@ -535,7 +535,7 @@ static void r4k_flush_data_cache_page(unsigned long addr)
                 local_r4k_flush_data_cache_page((void *)addr);
         else
                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
-                                1, 1);
+                                1);
 }
 
 struct flush_icache_range_args {
@@ -571,7 +571,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
         args.start = start;
         args.end = end;
 
-        r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1);
         instruction_hazard();
 }
 
@@ -672,7 +672,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 
 static void r4k_flush_cache_sigtramp(unsigned long addr)
 {
-        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
 }
 
 static void r4k_flush_icache_all(void)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 1edf0cbbeede..1417c6494858 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -235,13 +235,12 @@ static void __cpuinit set_prefetch_parameters(void)
         }
         /*
          * Too much unrolling will overflow the available space in
-         * clear_space_array / copy_page_array. 8 words sounds generous,
-         * but a R4000 with 128 byte L2 line length can exceed even that.
+         * clear_space_array / copy_page_array.
          */
-        half_clear_loop_size = min(8 * clear_word_size,
+        half_clear_loop_size = min(16 * clear_word_size,
                                    max(cache_line_size >> 1,
                                        4 * clear_word_size));
-        half_copy_loop_size = min(8 * copy_word_size,
+        half_copy_loop_size = min(16 * copy_word_size,
                                   max(cache_line_size >> 1,
                                       4 * copy_word_size));
 }
@@ -263,21 +262,23 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
         if (pref_bias_clear_store) {
                 uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
                             A0);
-        } else if (cpu_has_cache_cdex_s) {
-                uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
-        } else if (cpu_has_cache_cdex_p) {
-                if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                }
+        } else if (cache_line_size == (half_clear_loop_size << 1)) {
+                if (cpu_has_cache_cdex_s) {
+                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
+                } else if (cpu_has_cache_cdex_p) {
+                        if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                        }
 
-                if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                        uasm_i_lw(buf, ZERO, ZERO, AT);
+                        if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
-                uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
-        }
+                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                }
+                }
 }
 
 void __cpuinit build_clear_page(void)
@@ -403,20 +404,22 @@ static inline void build_copy_store_pref(u32 **buf, int off)
         if (pref_bias_copy_store) {
                 uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
                             A0);
-        } else if (cpu_has_cache_cdex_s) {
-                uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
-        } else if (cpu_has_cache_cdex_p) {
-                if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                }
+        } else if (cache_line_size == (half_copy_loop_size << 1)) {
+                if (cpu_has_cache_cdex_s) {
+                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
+                } else if (cpu_has_cache_cdex_p) {
+                        if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                        }
 
-                if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                        uasm_i_lw(buf, ZERO, ZERO, AT);
+                        if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
-                uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                }
         }
 }
 
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index fc227f3b1199..e3abfb2d7e86 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -86,7 +86,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
 /*
  * This function is executed in uncached address space.
  */
-static __init void __rm7k_sc_enable(void)
+static __cpuinit void __rm7k_sc_enable(void)
 {
         int i;
 
@@ -107,7 +107,7 @@ static __init void __rm7k_sc_enable(void)
         }
 }
 
-static __init void rm7k_sc_enable(void)
+static __cpuinit void rm7k_sc_enable(void)
 {
         if (read_c0_config() & RM7K_CONF_SE)
                 return;