diff options
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r-- | arch/mips/mm/uasm.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 4adf30284813..319051c34343 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c | |||
@@ -24,7 +24,8 @@ enum fields { | |||
24 | JIMM = 0x080, | 24 | JIMM = 0x080, |
25 | FUNC = 0x100, | 25 | FUNC = 0x100, |
26 | SET = 0x200, | 26 | SET = 0x200, |
27 | SCIMM = 0x400 | 27 | SCIMM = 0x400, |
28 | SIMM9 = 0x800, | ||
28 | }; | 29 | }; |
29 | 30 | ||
30 | #define OP_MASK 0x3f | 31 | #define OP_MASK 0x3f |
@@ -41,6 +42,8 @@ enum fields { | |||
41 | #define FUNC_SH 0 | 42 | #define FUNC_SH 0 |
42 | #define SET_MASK 0x7 | 43 | #define SET_MASK 0x7 |
43 | #define SET_SH 0 | 44 | #define SET_SH 0 |
45 | #define SIMM9_SH 7 | ||
46 | #define SIMM9_MASK 0x1ff | ||
44 | 47 | ||
45 | enum opcode { | 48 | enum opcode { |
46 | insn_invalid, | 49 | insn_invalid, |
@@ -116,6 +119,14 @@ static inline u32 build_scimm(u32 arg) | |||
116 | return (arg & SCIMM_MASK) << SCIMM_SH; | 119 | return (arg & SCIMM_MASK) << SCIMM_SH; |
117 | } | 120 | } |
118 | 121 | ||
122 | static inline u32 build_scimm9(s32 arg) | ||
123 | { | ||
124 | WARN((arg > 0xff || arg < -0x100), | ||
125 | KERN_WARNING "Micro-assembler field overflow\n"); | ||
126 | |||
127 | return (arg & SIMM9_MASK) << SIMM9_SH; | ||
128 | } | ||
129 | |||
119 | static inline u32 build_func(u32 arg) | 130 | static inline u32 build_func(u32 arg) |
120 | { | 131 | { |
121 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); | 132 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
@@ -330,7 +341,7 @@ I_u3u1u2(_ldx) | |||
330 | void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, | 341 | void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, |
331 | unsigned int c) | 342 | unsigned int c) |
332 | { | 343 | { |
333 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) | 344 | if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) |
334 | /* | 345 | /* |
335 | * As per erratum Core-14449, replace prefetches 0-4, | 346 | * As per erratum Core-14449, replace prefetches 0-4, |
336 | * 6-24 with 'pref 28'. | 347 | * 6-24 with 'pref 28'. |