1 files changed, 41 insertions, 29 deletions

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 59d38bc05b69..8297970f0bb1 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -21,6 +21,12 @@
 
 extern void build_tlb_refill_handler(void);
 
+/*
+ * Make sure all entries differ.  If they're not different
+ * MIPS32 will take revenge ...
+ */
+#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+
 /* CP0 hazard avoidance. */
 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
                                      "nop; nop; nop; nop; nop; nop;\n\t" \
@@ -42,11 +48,8 @@ void local_flush_tlb_all(void)
 
         /* Blast 'em all away. */
         while (entry < current_cpu_data.tlbsize) {
-                /*
-                 * Make sure all entries differ.  If they're not different
-                 * MIPS32 will take revenge ...
-                 */
-                write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
+                /* Make sure all entries differ. */
+                write_c0_entryhi(UNIQUE_ENTRYHI(entry));
                 write_c0_index(entry);
                 mtc0_tlbw_hazard();
                 tlb_write_indexed();
@@ -57,12 +60,21 @@ void local_flush_tlb_all(void)
         local_irq_restore(flags);
 }
 
+/* All entries common to a mm share an asid.  To effectively flush
+   these entries, we just bump the asid. */
 void local_flush_tlb_mm(struct mm_struct *mm)
 {
-        int cpu = smp_processor_id();
+        int cpu;
+
+        preempt_disable();
 
-        if (cpu_context(cpu, mm) != 0)
-                drop_mmu_context(mm,cpu);
+        cpu = smp_processor_id();
+
+        if (cpu_context(cpu, mm) != 0) {
+                drop_mmu_context(mm, cpu);
+        }
+
+        preempt_enable();
 }
 
 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -75,9 +87,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                 unsigned long flags;
                 int size;
 
-                local_irq_save(flags);
                 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
                 size = (size + 1) >> 1;
+                local_irq_save(flags);
                 if (size <= current_cpu_data.tlbsize/2) {
                         int oldpid = read_c0_entryhi();
                         int newpid = cpu_asid(cpu, mm);
@@ -99,8 +111,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                                 if (idx < 0)
                                         continue;
                                 /* Make sure all entries differ. */
-                                write_c0_entryhi(CKSEG0 +
-                                                 (idx << (PAGE_SHIFT + 1)));
+                                write_c0_entryhi(UNIQUE_ENTRYHI(idx));
                                 mtc0_tlbw_hazard();
                                 tlb_write_indexed();
                         }
@@ -118,9 +129,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
         unsigned long flags;
         int size;
 
-        local_irq_save(flags);
         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
         size = (size + 1) >> 1;
+        local_irq_save(flags);
         if (size <= current_cpu_data.tlbsize / 2) {
                 int pid = read_c0_entryhi();
 
@@ -142,7 +153,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
                         if (idx < 0)
                                 continue;
                         /* Make sure all entries differ. */
-                        write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
+                        write_c0_entryhi(UNIQUE_ENTRYHI(idx));
                         mtc0_tlbw_hazard();
                         tlb_write_indexed();
                 }
@@ -176,7 +187,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
                 if (idx < 0)
                         goto finish;
                 /* Make sure all entries differ. */
-                write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
+                write_c0_entryhi(UNIQUE_ENTRYHI(idx));
                 mtc0_tlbw_hazard();
                 tlb_write_indexed();
                 tlbw_use_hazard();
@@ -197,8 +208,8 @@ void local_flush_tlb_one(unsigned long page)
         int oldpid, idx;
 
         local_irq_save(flags);
-        page &= (PAGE_MASK << 1);
         oldpid = read_c0_entryhi();
+        page &= (PAGE_MASK << 1);
         write_c0_entryhi(page);
         mtc0_tlbw_hazard();
         tlb_probe();
@@ -208,7 +219,7 @@ void local_flush_tlb_one(unsigned long page)
         write_c0_entrylo1(0);
         if (idx >= 0) {
                 /* Make sure all entries differ. */
-                write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
+                write_c0_entryhi(UNIQUE_ENTRYHI(idx));
                 mtc0_tlbw_hazard();
                 tlb_write_indexed();
                 tlbw_use_hazard();
@@ -227,6 +238,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 {
         unsigned long flags;
         pgd_t *pgdp;
+        pud_t *pudp;
         pmd_t *pmdp;
         pte_t *ptep;
         int idx, pid;
@@ -237,35 +249,34 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
         if (current->active_mm != vma->vm_mm)
                 return;
 
-        pid = read_c0_entryhi() & ASID_MASK;
-
         local_irq_save(flags);
+
+        pid = read_c0_entryhi() & ASID_MASK;
         address &= (PAGE_MASK << 1);
         write_c0_entryhi(address | pid);
         pgdp = pgd_offset(vma->vm_mm, address);
         mtc0_tlbw_hazard();
         tlb_probe();
         BARRIER;
-        pmdp = pmd_offset(pgdp, address);
+        pudp = pud_offset(pgdp, address);
+        pmdp = pmd_offset(pudp, address);
         idx = read_c0_index();
         ptep = pte_offset_map(pmdp, address);
 
- #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-        write_c0_entrylo0(ptep->pte_high);
-        ptep++;
-        write_c0_entrylo1(ptep->pte_high);
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+        write_c0_entrylo0(ptep->pte_high);
+        ptep++;
+        write_c0_entrylo1(ptep->pte_high);
 #else
-        write_c0_entrylo0(pte_val(*ptep++) >> 6);
-        write_c0_entrylo1(pte_val(*ptep) >> 6);
+        write_c0_entrylo0(pte_val(*ptep++) >> 6);
+        write_c0_entrylo1(pte_val(*ptep) >> 6);
 #endif
-        write_c0_entryhi(address | pid);
         mtc0_tlbw_hazard();
         if (idx < 0)
                 tlb_write_random();
         else
                 tlb_write_indexed();
         tlbw_use_hazard();
-        write_c0_entryhi(pid);
         local_irq_restore(flags);
 }
 
@@ -357,7 +368,8 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
         old_pagemask = read_c0_pagemask();
         wired = read_c0_wired();
         if (--temp_tlb_entry < wired) {
-                printk(KERN_WARNING "No TLB space left for add_temporary_entry\n");
+                printk(KERN_WARNING
+                       "No TLB space left for add_temporary_entry\n");
                 ret = -ENOSPC;
                 goto out;
         }
@@ -388,7 +400,7 @@ static void __init probe_tlb(unsigned long config)
          * is not supported, we assume R4k style.  Cpu probing already figured
          * out the number of tlb entries.
          */
-        if ((c->processor_id  & 0xff0000) == PRID_COMP_LEGACY)
+        if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
                 return;
 
         reg = read_c0_config1();