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-rw-r--r--arch/mips/mm/pg-r4k.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index f51e180072e3..e4390dc3eb48 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -124,7 +124,7 @@ static inline void build_nop(void)
124 124
125static inline void build_src_pref(int advance) 125static inline void build_src_pref(int advance)
126{ 126{
127 if (!(load_offset & (cpu_dcache_line_size() - 1))) { 127 if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
128 union mips_instruction mi; 128 union mips_instruction mi;
129 129
130 mi.i_format.opcode = pref_op; 130 mi.i_format.opcode = pref_op;
@@ -166,7 +166,7 @@ static inline void build_load_reg(int reg)
166 166
167static inline void build_dst_pref(int advance) 167static inline void build_dst_pref(int advance)
168{ 168{
169 if (!(store_offset & (cpu_dcache_line_size() - 1))) { 169 if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
170 union mips_instruction mi; 170 union mips_instruction mi;
171 171
172 mi.i_format.opcode = pref_op; 172 mi.i_format.opcode = pref_op;
@@ -340,6 +340,12 @@ void __init build_clear_page(void)
340 340
341 if (cpu_has_prefetch) { 341 if (cpu_has_prefetch) {
342 switch (current_cpu_data.cputype) { 342 switch (current_cpu_data.cputype) {
343 case CPU_TX49XX:
344 /* TX49 supports only Pref_Load */
345 pref_offset_clear = 0;
346 pref_offset_copy = 0;
347 break;
348
343 case CPU_RM9000: 349 case CPU_RM9000:
344 /* 350 /*
345 * As a workaround for erratum G105 which make the 351 * As a workaround for erratum G105 which make the