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Diffstat (limited to 'arch/mips/mm/c-tx39.c')
-rw-r--r--arch/mips/mm/c-tx39.c70
1 files changed, 9 insertions, 61 deletions
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 0a97a9434eba..7c572bea4a98 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -44,8 +44,6 @@ __asm__ __volatile__( \
44/* TX39H-style cache flush routines. */ 44/* TX39H-style cache flush routines. */
45static void tx39h_flush_icache_all(void) 45static void tx39h_flush_icache_all(void)
46{ 46{
47 unsigned long start = KSEG0;
48 unsigned long end = (start + icache_size);
49 unsigned long flags, config; 47 unsigned long flags, config;
50 48
51 /* disable icache (set ICE#) */ 49 /* disable icache (set ICE#) */
@@ -53,33 +51,18 @@ static void tx39h_flush_icache_all(void)
53 config = read_c0_conf(); 51 config = read_c0_conf();
54 write_c0_conf(config & ~TX39_CONF_ICE); 52 write_c0_conf(config & ~TX39_CONF_ICE);
55 TX39_STOP_STREAMING(); 53 TX39_STOP_STREAMING();
56 54 blast_icache16();
57 /* invalidate icache */
58 while (start < end) {
59 cache16_unroll32(start, Index_Invalidate_I);
60 start += 0x200;
61 }
62
63 write_c0_conf(config); 55 write_c0_conf(config);
64 local_irq_restore(flags); 56 local_irq_restore(flags);
65} 57}
66 58
67static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) 59static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
68{ 60{
69 unsigned long end, a;
70 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
71
72 /* Catch bad driver code */ 61 /* Catch bad driver code */
73 BUG_ON(size == 0); 62 BUG_ON(size == 0);
74 63
75 iob(); 64 iob();
76 a = addr & ~(dc_lsize - 1); 65 blast_inv_dcache_range(addr, addr + size);
77 end = (addr + size - 1) & ~(dc_lsize - 1);
78 while (1) {
79 invalidate_dcache_line(a); /* Hit_Invalidate_D */
80 if (a == end) break;
81 a += dc_lsize;
82 }
83} 66}
84 67
85 68
@@ -241,42 +224,21 @@ static void tx39_flush_data_cache_page(unsigned long addr)
241 224
242static void tx39_flush_icache_range(unsigned long start, unsigned long end) 225static void tx39_flush_icache_range(unsigned long start, unsigned long end)
243{ 226{
244 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
245 unsigned long addr, aend;
246
247 if (end - start > dcache_size) 227 if (end - start > dcache_size)
248 tx39_blast_dcache(); 228 tx39_blast_dcache();
249 else { 229 else
250 addr = start & ~(dc_lsize - 1); 230 protected_blast_dcache_range(start, end);
251 aend = (end - 1) & ~(dc_lsize - 1);
252
253 while (1) {
254 /* Hit_Writeback_Inv_D */
255 protected_writeback_dcache_line(addr);
256 if (addr == aend)
257 break;
258 addr += dc_lsize;
259 }
260 }
261 231
262 if (end - start > icache_size) 232 if (end - start > icache_size)
263 tx39_blast_icache(); 233 tx39_blast_icache();
264 else { 234 else {
265 unsigned long flags, config; 235 unsigned long flags, config;
266 addr = start & ~(dc_lsize - 1);
267 aend = (end - 1) & ~(dc_lsize - 1);
268 /* disable icache (set ICE#) */ 236 /* disable icache (set ICE#) */
269 local_irq_save(flags); 237 local_irq_save(flags);
270 config = read_c0_conf(); 238 config = read_c0_conf();
271 write_c0_conf(config & ~TX39_CONF_ICE); 239 write_c0_conf(config & ~TX39_CONF_ICE);
272 TX39_STOP_STREAMING(); 240 TX39_STOP_STREAMING();
273 while (1) { 241 protected_blast_icache_range(start, end);
274 /* Hit_Invalidate_I */
275 protected_flush_icache_line(addr);
276 if (addr == aend)
277 break;
278 addr += dc_lsize;
279 }
280 write_c0_conf(config); 242 write_c0_conf(config);
281 local_irq_restore(flags); 243 local_irq_restore(flags);
282 } 244 }
@@ -311,7 +273,7 @@ static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page
311 273
312static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size) 274static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
313{ 275{
314 unsigned long end, a; 276 unsigned long end;
315 277
316 if (((size | addr) & (PAGE_SIZE - 1)) == 0) { 278 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
317 end = addr + size; 279 end = addr + size;
@@ -322,20 +284,13 @@ static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
322 } else if (size > dcache_size) { 284 } else if (size > dcache_size) {
323 tx39_blast_dcache(); 285 tx39_blast_dcache();
324 } else { 286 } else {
325 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 287 blast_dcache_range(addr, addr + size);
326 a = addr & ~(dc_lsize - 1);
327 end = (addr + size - 1) & ~(dc_lsize - 1);
328 while (1) {
329 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
330 if (a == end) break;
331 a += dc_lsize;
332 }
333 } 288 }
334} 289}
335 290
336static void tx39_dma_cache_inv(unsigned long addr, unsigned long size) 291static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
337{ 292{
338 unsigned long end, a; 293 unsigned long end;
339 294
340 if (((size | addr) & (PAGE_SIZE - 1)) == 0) { 295 if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
341 end = addr + size; 296 end = addr + size;
@@ -346,14 +301,7 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
346 } else if (size > dcache_size) { 301 } else if (size > dcache_size) {
347 tx39_blast_dcache(); 302 tx39_blast_dcache();
348 } else { 303 } else {
349 unsigned long dc_lsize = current_cpu_data.dcache.linesz; 304 blast_inv_dcache_range(addr, addr + size);
350 a = addr & ~(dc_lsize - 1);
351 end = (addr + size - 1) & ~(dc_lsize - 1);
352 while (1) {
353 invalidate_dcache_line(a); /* Hit_Invalidate_D */
354 if (a == end) break;
355 a += dc_lsize;
356 }
357 } 305 }
358} 306}
359 307