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-rw-r--r--arch/mips/mm/c-tx39.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 87d23cada6d6..ba9da270289f 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -33,9 +33,9 @@ extern int r3k_have_wired_reg; /* in r3k-tlb.c */
33/* This sequence is required to ensure icache is disabled immediately */ 33/* This sequence is required to ensure icache is disabled immediately */
34#define TX39_STOP_STREAMING() \ 34#define TX39_STOP_STREAMING() \
35__asm__ __volatile__( \ 35__asm__ __volatile__( \
36 ".set push\n\t" \ 36 ".set push\n\t" \
37 ".set noreorder\n\t" \ 37 ".set noreorder\n\t" \
38 "b 1f\n\t" \ 38 "b 1f\n\t" \
39 "nop\n\t" \ 39 "nop\n\t" \
40 "1:\n\t" \ 40 "1:\n\t" \
41 ".set pop" \ 41 ".set pop" \
@@ -361,7 +361,7 @@ void __cpuinit tx39_cache_init(void)
361 /* TX39/H core (writethru direct-map cache) */ 361 /* TX39/H core (writethru direct-map cache) */
362 __flush_cache_vmap = tx39__flush_cache_vmap; 362 __flush_cache_vmap = tx39__flush_cache_vmap;
363 __flush_cache_vunmap = tx39__flush_cache_vunmap; 363 __flush_cache_vunmap = tx39__flush_cache_vunmap;
364 flush_cache_all = tx39h_flush_icache_all; 364 flush_cache_all = tx39h_flush_icache_all;
365 __flush_cache_all = tx39h_flush_icache_all; 365 __flush_cache_all = tx39h_flush_icache_all;
366 flush_cache_mm = (void *) tx39h_flush_icache_all; 366 flush_cache_mm = (void *) tx39h_flush_icache_all;
367 flush_cache_range = (void *) tx39h_flush_icache_all; 367 flush_cache_range = (void *) tx39h_flush_icache_all;
@@ -409,8 +409,8 @@ void __cpuinit tx39_cache_init(void)
409 _dma_cache_inv = tx39_dma_cache_inv; 409 _dma_cache_inv = tx39_dma_cache_inv;
410 410
411 shm_align_mask = max_t(unsigned long, 411 shm_align_mask = max_t(unsigned long,
412 (dcache_size / current_cpu_data.dcache.ways) - 1, 412 (dcache_size / current_cpu_data.dcache.ways) - 1,
413 PAGE_SIZE - 1); 413 PAGE_SIZE - 1);
414 414
415 break; 415 break;
416 } 416 }