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-rw-r--r--arch/mips/mm/c-sb1.c61
1 files changed, 0 insertions, 61 deletions
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 16bad7c0a63f..5537558f19f7 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -307,66 +307,6 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end)
307#endif 307#endif
308 308
309/* 309/*
310 * Flush the icache for a given physical page. Need to writeback the
311 * dcache first, then invalidate the icache. If the page isn't
312 * executable, nothing is required.
313 */
314static void local_sb1_flush_icache_page(struct vm_area_struct *vma,
315 struct page *page)
316{
317 unsigned long start;
318 int cpu = smp_processor_id();
319
320#ifndef CONFIG_SMP
321 if (!(vma->vm_flags & VM_EXEC))
322 return;
323#endif
324
325 /* Need to writeback any dirty data for that page, we have the PA */
326 start = (unsigned long)(page-mem_map) << PAGE_SHIFT;
327 __sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE);
328 /*
329 * If there's a context, bump the ASID (cheaper than a flush,
330 * since we don't know VAs!)
331 */
332 if (vma->vm_mm == current->active_mm) {
333 if (cpu_context(cpu, vma->vm_mm) != 0)
334 drop_mmu_context(vma->vm_mm, cpu);
335 } else
336 __sb1_flush_icache_range(start, start + PAGE_SIZE);
337
338}
339
340#ifdef CONFIG_SMP
341struct flush_icache_page_args {
342 struct vm_area_struct *vma;
343 struct page *page;
344};
345
346static void sb1_flush_icache_page_ipi(void *info)
347{
348 struct flush_icache_page_args *args = info;
349 local_sb1_flush_icache_page(args->vma, args->page);
350}
351
352/* Dirty dcache could be on another CPU, so do the IPIs */
353static void sb1_flush_icache_page(struct vm_area_struct *vma,
354 struct page *page)
355{
356 struct flush_icache_page_args args;
357
358 if (!(vma->vm_flags & VM_EXEC))
359 return;
360 args.vma = vma;
361 args.page = page;
362 on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1);
363}
364#else
365void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
366 __attribute__((alias("local_sb1_flush_icache_page")));
367#endif
368
369/*
370 * A signal trampoline must fit into a single cacheline. 310 * A signal trampoline must fit into a single cacheline.
371 */ 311 */
372static void local_sb1_flush_cache_sigtramp(unsigned long addr) 312static void local_sb1_flush_cache_sigtramp(unsigned long addr)
@@ -526,7 +466,6 @@ void sb1_cache_init(void)
526 466
527 /* These routines are for Icache coherence with the Dcache */ 467 /* These routines are for Icache coherence with the Dcache */
528 flush_icache_range = sb1_flush_icache_range; 468 flush_icache_range = sb1_flush_icache_range;
529 __flush_icache_page = sb1_flush_icache_page;
530 flush_icache_all = __sb1_flush_icache_all; /* local only */ 469 flush_icache_all = __sb1_flush_icache_all; /* local only */
531 470
532 /* This implies an Icache flush too, so can't be nop'ed */ 471 /* This implies an Icache flush too, so can't be nop'ed */