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-rw-r--r--arch/mips/mm/c-r4k.c26
1 files changed, 18 insertions, 8 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 49e572d879e1..c14259edd53f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1020,10 +1020,14 @@ static void probe_pcache(void)
1020 */ 1020 */
1021 config1 = read_c0_config1(); 1021 config1 = read_c0_config1();
1022 1022
1023 if ((lsize = ((config1 >> 19) & 7))) 1023 lsize = (config1 >> 19) & 7;
1024 c->icache.linesz = 2 << lsize; 1024
1025 else 1025 /* IL == 7 is reserved */
1026 c->icache.linesz = lsize; 1026 if (lsize == 7)
1027 panic("Invalid icache line size");
1028
1029 c->icache.linesz = lsize ? 2 << lsize : 0;
1030
1027 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1031 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1028 c->icache.ways = 1 + ((config1 >> 16) & 7); 1032 c->icache.ways = 1 + ((config1 >> 16) & 7);
1029 1033
@@ -1040,10 +1044,14 @@ static void probe_pcache(void)
1040 */ 1044 */
1041 c->dcache.flags = 0; 1045 c->dcache.flags = 0;
1042 1046
1043 if ((lsize = ((config1 >> 10) & 7))) 1047 lsize = (config1 >> 10) & 7;
1044 c->dcache.linesz = 2 << lsize; 1048
1045 else 1049 /* DL == 7 is reserved */
1046 c->dcache.linesz= lsize; 1050 if (lsize == 7)
1051 panic("Invalid dcache line size");
1052
1053 c->dcache.linesz = lsize ? 2 << lsize : 0;
1054
1047 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1055 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1048 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1056 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1049 1057
@@ -1105,6 +1113,8 @@ static void probe_pcache(void)
1105 case CPU_34K: 1113 case CPU_34K:
1106 case CPU_74K: 1114 case CPU_74K:
1107 case CPU_1004K: 1115 case CPU_1004K:
1116 case CPU_INTERAPTIV:
1117 case CPU_PROAPTIV:
1108 if (current_cpu_type() == CPU_74K) 1118 if (current_cpu_type() == CPU_74K)
1109 alias_74k_erratum(c); 1119 alias_74k_erratum(c);
1110 if ((read_c0_config7() & (1 << 16))) { 1120 if ((read_c0_config7() & (1 << 16))) {