1 files changed, 4 insertions, 2 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index dd261df005c2..3f8059602765 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -794,7 +794,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
                 __asm__ __volatile__ (
                         ".set push\n\t"
                         ".set noat\n\t"
-                        ".set mips3\n\t"
+                        ".set "MIPS_ISA_LEVEL"\n\t"
 #ifdef CONFIG_32BIT
                         "la     $at,1f\n\t"
 #endif
@@ -1255,6 +1255,7 @@ static void probe_pcache(void)
         case CPU_P5600:
         case CPU_PROAPTIV:
         case CPU_M5150:
+        case CPU_QEMU_GENERIC:
                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
                     (c->icache.waysize > PAGE_SIZE))
                         c->icache.flags |= MIPS_CACHE_ALIASES;
@@ -1472,7 +1473,8 @@ static void setup_scache(void)
 
         default:
                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
-                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
+                                    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
+                                    MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;