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-rw-r--r--arch/mips/mm/c-r4k.c17
1 files changed, 5 insertions, 12 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9355f1c9325f..02bd180f0e02 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -449,7 +449,7 @@ static inline void local_r4k_flush_cache_page(void *args)
449 * If the page isn't marked valid, the page cannot possibly be 449 * If the page isn't marked valid, the page cannot possibly be
450 * in the cache. 450 * in the cache.
451 */ 451 */
452 if (!(pte_val(*ptep) & _PAGE_PRESENT)) 452 if (!(pte_present(*ptep)))
453 return; 453 return;
454 454
455 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 455 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
@@ -468,8 +468,6 @@ static inline void local_r4k_flush_cache_page(void *args)
468 468
469 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 469 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
470 r4k_blast_dcache_page(addr); 470 r4k_blast_dcache_page(addr);
471 if (exec && !cpu_icache_snoops_remote_store)
472 r4k_blast_scache_page(addr);
473 } 471 }
474 if (exec) { 472 if (exec) {
475 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 473 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
@@ -533,13 +531,6 @@ static inline void local_r4k_flush_icache_range(void *args)
533 R4600_HIT_CACHEOP_WAR_IMPL; 531 R4600_HIT_CACHEOP_WAR_IMPL;
534 protected_blast_dcache_range(start, end); 532 protected_blast_dcache_range(start, end);
535 } 533 }
536
537 if (!cpu_icache_snoops_remote_store && scache_size) {
538 if (end - start > scache_size)
539 r4k_blast_scache();
540 else
541 protected_blast_scache_range(start, end);
542 }
543 } 534 }
544 535
545 if (end - start > icache_size) 536 if (end - start > icache_size)
@@ -598,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
598 if (size >= scache_size) 589 if (size >= scache_size)
599 r4k_blast_scache(); 590 r4k_blast_scache();
600 else 591 else
601 blast_scache_range(addr, addr + size); 592 blast_inv_scache_range(addr, addr + size);
602 return; 593 return;
603 } 594 }
604 595
@@ -606,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
606 r4k_blast_dcache(); 597 r4k_blast_dcache();
607 } else { 598 } else {
608 R4600_HIT_CACHEOP_WAR_IMPL; 599 R4600_HIT_CACHEOP_WAR_IMPL;
609 blast_dcache_range(addr, addr + size); 600 blast_inv_dcache_range(addr, addr + size);
610 } 601 }
611 602
612 bc_inv(addr, size); 603 bc_inv(addr, size);
@@ -989,6 +980,8 @@ static void __init probe_pcache(void)
989 case CPU_AU1100: 980 case CPU_AU1100:
990 case CPU_AU1550: 981 case CPU_AU1550:
991 case CPU_AU1200: 982 case CPU_AU1200:
983 case CPU_AU1210:
984 case CPU_AU1250:
992 c->icache.flags |= MIPS_CACHE_IC_F_DC; 985 c->icache.flags |= MIPS_CACHE_IC_F_DC;
993 break; 986 break;
994 } 987 }