aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mm/c-r4k.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c77
1 files changed, 0 insertions, 77 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0b2da53750bd..cc895dad71d2 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -551,82 +551,6 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
551 instruction_hazard(); 551 instruction_hazard();
552} 552}
553 553
554/*
555 * Ok, this seriously sucks. We use them to flush a user page but don't
556 * know the virtual address, so we have to blast away the whole icache
557 * which is significantly more expensive than the real thing. Otoh we at
558 * least know the kernel address of the page so we can flush it
559 * selectivly.
560 */
561
562struct flush_icache_page_args {
563 struct vm_area_struct *vma;
564 struct page *page;
565};
566
567static inline void local_r4k_flush_icache_page(void *args)
568{
569 struct flush_icache_page_args *fip_args = args;
570 struct vm_area_struct *vma = fip_args->vma;
571 struct page *page = fip_args->page;
572
573 /*
574 * Tricky ... Because we don't know the virtual address we've got the
575 * choice of either invalidating the entire primary and secondary
576 * caches or invalidating the secondary caches also. With the subset
577 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
578 * secondary cache will result in any entries in the primary caches
579 * also getting invalidated which hopefully is a bit more economical.
580 */
581 if (cpu_has_inclusive_pcaches) {
582 unsigned long addr = (unsigned long) page_address(page);
583
584 r4k_blast_scache_page(addr);
585 ClearPageDcacheDirty(page);
586
587 return;
588 }
589
590 if (!cpu_has_ic_fills_f_dc) {
591 unsigned long addr = (unsigned long) page_address(page);
592 r4k_blast_dcache_page(addr);
593 if (!cpu_icache_snoops_remote_store)
594 r4k_blast_scache_page(addr);
595 ClearPageDcacheDirty(page);
596 }
597
598 /*
599 * We're not sure of the virtual address(es) involved here, so
600 * we have to flush the entire I-cache.
601 */
602 if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) {
603 int cpu = smp_processor_id();
604
605 if (cpu_context(cpu, vma->vm_mm) != 0)
606 drop_mmu_context(vma->vm_mm, cpu);
607 } else
608 r4k_blast_icache();
609}
610
611static void r4k_flush_icache_page(struct vm_area_struct *vma,
612 struct page *page)
613{
614 struct flush_icache_page_args args;
615
616 /*
617 * If there's no context yet, or the page isn't executable, no I-cache
618 * flush is needed.
619 */
620 if (!(vma->vm_flags & VM_EXEC))
621 return;
622
623 args.vma = vma;
624 args.page = page;
625
626 r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
627}
628
629
630#ifdef CONFIG_DMA_NONCOHERENT 554#ifdef CONFIG_DMA_NONCOHERENT
631 555
632static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 556static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
@@ -1291,7 +1215,6 @@ void __init r4k_cache_init(void)
1291 __flush_cache_all = r4k___flush_cache_all; 1215 __flush_cache_all = r4k___flush_cache_all;
1292 flush_cache_mm = r4k_flush_cache_mm; 1216 flush_cache_mm = r4k_flush_cache_mm;
1293 flush_cache_page = r4k_flush_cache_page; 1217 flush_cache_page = r4k_flush_cache_page;
1294 __flush_icache_page = r4k_flush_icache_page;
1295 flush_cache_range = r4k_flush_cache_range; 1218 flush_cache_range = r4k_flush_cache_range;
1296 1219
1297 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1220 flush_cache_sigtramp = r4k_flush_cache_sigtramp;