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-rw-r--r--arch/mips/mipssim/Makefile24
-rw-r--r--arch/mips/mipssim/sim_cmdline.c35
-rw-r--r--arch/mips/mipssim/sim_console.c40
-rw-r--r--arch/mips/mipssim/sim_int.c88
-rw-r--r--arch/mips/mipssim/sim_mem.c115
-rw-r--r--arch/mips/mipssim/sim_platform.c35
-rw-r--r--arch/mips/mipssim/sim_setup.c98
-rw-r--r--arch/mips/mipssim/sim_smp.c123
-rw-r--r--arch/mips/mipssim/sim_time.c200
9 files changed, 758 insertions, 0 deletions
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
new file mode 100644
index 000000000000..dc0bfda11427
--- /dev/null
+++ b/arch/mips/mipssim/Makefile
@@ -0,0 +1,24 @@
1#
2# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3# Copyright (C) 2007 MIPS Technologies, Inc.
4# written by Ralf Baechle (ralf@linux-mips.org)
5#
6# This program is free software; you can distribute it and/or modify it
7# under the terms of the GNU General Public License (Version 2) as
8# published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13# for more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program; if not, write to the Free Software Foundation, Inc.,
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18#
19
20obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \
21 sim_cmdline.o
22
23obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
24obj-$(CONFIG_SMP) += sim_smp.o
diff --git a/arch/mips/mipssim/sim_cmdline.c b/arch/mips/mipssim/sim_cmdline.c
new file mode 100644
index 000000000000..c63021a5dc6c
--- /dev/null
+++ b/arch/mips/mipssim/sim_cmdline.c
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/string.h>
20#include <asm/bootinfo.h>
21
22extern char arcs_cmdline[];
23
24char * __init prom_getcmdline(void)
25{
26 return arcs_cmdline;
27}
28
29void __init prom_init_cmdline(void)
30{
31 char *cp;
32 cp = arcs_cmdline;
33 /* Get boot line from environment? */
34 *cp = '\0';
35}
diff --git a/arch/mips/mipssim/sim_console.c b/arch/mips/mipssim/sim_console.c
new file mode 100644
index 000000000000..a2f41672cd5d
--- /dev/null
+++ b/arch/mips/mipssim/sim_console.c
@@ -0,0 +1,40 @@
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 *
15 * Carsten Langgaard, carstenl@mips.com
16 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
17 * Copyright (C) 2007 MIPS Technologies, Inc.
18 * written by Ralf Baechle
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/serial_reg.h>
23
24static inline unsigned int serial_in(int offset)
25{
26 return inb(0x3f8 + offset);
27}
28
29static inline void serial_out(int offset, int value)
30{
31 outb(value, 0x3f8 + offset);
32}
33
34void __init prom_putchar(char c)
35{
36 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
37 ;
38
39 serial_out(UART_TX, c);
40}
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
new file mode 100644
index 000000000000..d86b37235cf6
--- /dev/null
+++ b/arch/mips/mipssim/sim_int.c
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/interrupt.h>
22#include <linux/kernel_stat.h>
23#include <asm/mips-boards/simint.h>
24#include <asm/irq_cpu.h>
25
26static inline int clz(unsigned long x)
27{
28 __asm__ (
29 " .set push \n"
30 " .set mips32 \n"
31 " clz %0, %1 \n"
32 " .set pop \n"
33 : "=r" (x)
34 : "r" (x));
35
36 return x;
37}
38
39/*
40 * Version of ffs that only looks at bits 12..15.
41 */
42static inline unsigned int irq_ffs(unsigned int pending)
43{
44#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
45 return -clz(pending) + 31 - CAUSEB_IP;
46#else
47 unsigned int a0 = 7;
48 unsigned int t0;
49
50 t0 = s0 & 0xf000;
51 t0 = t0 < 1;
52 t0 = t0 << 2;
53 a0 = a0 - t0;
54 s0 = s0 << t0;
55
56 t0 = s0 & 0xc000;
57 t0 = t0 < 1;
58 t0 = t0 << 1;
59 a0 = a0 - t0;
60 s0 = s0 << t0;
61
62 t0 = s0 & 0x8000;
63 t0 = t0 < 1;
64 /* t0 = t0 << 2; */
65 a0 = a0 - t0;
66 /* s0 = s0 << t0; */
67
68 return a0;
69#endif
70}
71
72asmlinkage void plat_irq_dispatch(void)
73{
74 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
75 int irq;
76
77 irq = irq_ffs(pending);
78
79 if (irq > 0)
80 do_IRQ(MIPSCPU_INT_BASE + irq);
81 else
82 spurious_interrupt();
83}
84
85void __init arch_init_irq(void)
86{
87 mips_cpu_irq_init();
88}
diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
new file mode 100644
index 000000000000..2312483eb838
--- /dev/null
+++ b/arch/mips/mipssim/sim_mem.c
@@ -0,0 +1,115 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/bootmem.h>
21#include <linux/pfn.h>
22
23#include <asm/bootinfo.h>
24#include <asm/page.h>
25#include <asm/sections.h>
26
27#include <asm/mips-boards/prom.h>
28
29/*#define DEBUG*/
30
31enum simmem_memtypes {
32 simmem_reserved = 0,
33 simmem_free,
34};
35struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
36
37#ifdef DEBUG
38static char *mtypes[3] = {
39 "SIM reserved memory",
40 "SIM free memory",
41};
42#endif
43
44struct prom_pmemblock * __init prom_getmdesc(void)
45{
46 unsigned int memsize;
47
48 memsize = 0x02000000;
49 pr_info("Setting default memory size 0x%08x\n", memsize);
50
51 memset(mdesc, 0, sizeof(mdesc));
52
53 mdesc[0].type = simmem_reserved;
54 mdesc[0].base = 0x00000000;
55 mdesc[0].size = 0x00001000;
56
57 mdesc[1].type = simmem_free;
58 mdesc[1].base = 0x00001000;
59 mdesc[1].size = 0x000ff000;
60
61 mdesc[2].type = simmem_reserved;
62 mdesc[2].base = 0x00100000;
63 mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base;
64
65 mdesc[3].type = simmem_free;
66 mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end));
67 mdesc[3].size = memsize - mdesc[3].base;
68
69 return &mdesc[0];
70}
71
72static int __init prom_memtype_classify (unsigned int type)
73{
74 switch (type) {
75 case simmem_free:
76 return BOOT_MEM_RAM;
77 case simmem_reserved:
78 default:
79 return BOOT_MEM_RESERVED;
80 }
81}
82
83void __init prom_meminit(void)
84{
85 struct prom_pmemblock *p;
86
87 p = prom_getmdesc();
88
89 while (p->size) {
90 long type;
91 unsigned long base, size;
92
93 type = prom_memtype_classify (p->type);
94 base = p->base;
95 size = p->size;
96
97 add_memory_region(base, size, type);
98 p++;
99 }
100}
101
102void __init prom_free_prom_memory(void)
103{
104 int i;
105 unsigned long addr;
106
107 for (i = 0; i < boot_mem_map.nr_map; i++) {
108 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
109 continue;
110
111 addr = boot_mem_map.map[i].addr;
112 free_init_pages("prom memory",
113 addr, addr + boot_mem_map.map[i].size);
114 }
115}
diff --git a/arch/mips/mipssim/sim_platform.c b/arch/mips/mipssim/sim_platform.c
new file mode 100644
index 000000000000..53210a8c5dec
--- /dev/null
+++ b/arch/mips/mipssim/sim_platform.c
@@ -0,0 +1,35 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/if_ether.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12
13static char mipsnet_string[] = "mipsnet";
14
15static struct platform_device eth1_device = {
16 .name = mipsnet_string,
17 .id = 0,
18};
19
20/*
21 * Create a platform device for the GPI port that receives the
22 * image data from the embedded camera.
23 */
24static int __init mipsnet_devinit(void)
25{
26 int err;
27
28 err = platform_device_register(&eth1_device);
29 if (err)
30 printk(KERN_ERR "%s: registration failed\n", mipsnet_string);
31
32 return err;
33}
34
35device_initcall(mipsnet_devinit);
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
new file mode 100644
index 000000000000..3643582bdade
--- /dev/null
+++ b/arch/mips/mipssim/sim_setup.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#include <linux/init.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/ioport.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/serial.h>
28#include <linux/serial_core.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/mips-boards/generic.h>
33#include <asm/mips-boards/prom.h>
34#include <asm/time.h>
35#include <asm/mips-boards/sim.h>
36#include <asm/mips-boards/simint.h>
37
38
39extern void sim_time_init(void);
40static void __init serial_init(void);
41unsigned int _isbonito = 0;
42
43extern void __init sanitize_tlb_entries(void);
44
45
46const char *get_system_type(void)
47{
48 return "MIPSsim";
49}
50
51void __init plat_mem_setup(void)
52{
53 set_io_port_base(0xbfd00000);
54
55 serial_init();
56
57 board_time_init = sim_time_init;
58 pr_info("Linux started...\n");
59
60#ifdef CONFIG_MIPS_MT_SMP
61 sanitize_tlb_entries();
62#endif
63}
64
65void __init prom_init(void)
66{
67 set_io_port_base(0xbfd00000);
68
69 pr_info("\nLINUX started...\n");
70 prom_init_cmdline();
71 prom_meminit();
72}
73
74
75static void __init serial_init(void)
76{
77#ifdef CONFIG_SERIAL_8250
78 struct uart_port s;
79
80 memset(&s, 0, sizeof(s));
81
82 s.iobase = 0x3f8;
83
84 /* hardware int 4 - the serial int, is CPU int 6
85 but poll for now */
86 s.irq = 0;
87 s.uartclk = BASE_BAUD * 16;
88 s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
89 s.iotype = UPIO_PORT;
90 s.regshift = 0;
91 s.timeout = 4;
92
93 if (early_serial_setup(&s) != 0) {
94 printk(KERN_ERR "Serial setup failed!\n");
95 }
96
97#endif
98}
diff --git a/arch/mips/mipssim/sim_smp.c b/arch/mips/mipssim/sim_smp.c
new file mode 100644
index 000000000000..38fa807b99f9
--- /dev/null
+++ b/arch/mips/mipssim/sim_smp.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18/*
19 * Simulator Platform-specific hooks for SMP operation
20 */
21#include <linux/kernel.h>
22#include <linux/sched.h>
23#include <linux/cpumask.h>
24#include <linux/interrupt.h>
25#include <linux/smp.h>
26
27#include <asm/atomic.h>
28#include <asm/cpu.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/mmu_context.h>
32#ifdef CONFIG_MIPS_MT_SMTC
33#include <asm/smtc_ipi.h>
34#endif /* CONFIG_MIPS_MT_SMTC */
35
36/* VPE/SMP Prototype implements platform interfaces directly */
37#if !defined(CONFIG_MIPS_MT_SMP)
38
39/*
40 * Cause the specified action to be performed on a targeted "CPU"
41 */
42
43void core_send_ipi(int cpu, unsigned int action)
44{
45#ifdef CONFIG_MIPS_MT_SMTC
46 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
47#endif /* CONFIG_MIPS_MT_SMTC */
48/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
49
50}
51
52/*
53 * Platform "CPU" startup hook
54 */
55
56void prom_boot_secondary(int cpu, struct task_struct *idle)
57{
58#ifdef CONFIG_MIPS_MT_SMTC
59 smtc_boot_secondary(cpu, idle);
60#endif /* CONFIG_MIPS_MT_SMTC */
61}
62
63/*
64 * Post-config but pre-boot cleanup entry point
65 */
66
67void prom_init_secondary(void)
68{
69#ifdef CONFIG_MIPS_MT_SMTC
70 void smtc_init_secondary(void);
71
72 smtc_init_secondary();
73#endif /* CONFIG_MIPS_MT_SMTC */
74}
75
76void plat_smp_setup(void)
77{
78#ifdef CONFIG_MIPS_MT_SMTC
79 if (read_c0_config3() & (1 << 2))
80 mipsmt_build_cpu_map(0);
81#endif /* CONFIG_MIPS_MT_SMTC */
82}
83
84/*
85 * Platform SMP pre-initialization
86 */
87
88void plat_prepare_cpus(unsigned int max_cpus)
89{
90#ifdef CONFIG_MIPS_MT_SMTC
91 /*
92 * As noted above, we can assume a single CPU for now
93 * but it may be multithreaded.
94 */
95
96 if (read_c0_config3() & (1 << 2)) {
97 mipsmt_prepare_cpus();
98 }
99#endif /* CONFIG_MIPS_MT_SMTC */
100}
101
102/*
103 * SMP initialization finalization entry point
104 */
105
106void prom_smp_finish(void)
107{
108#ifdef CONFIG_MIPS_MT_SMTC
109 smtc_smp_finish();
110#endif /* CONFIG_MIPS_MT_SMTC */
111}
112
113/*
114 * Hook for after all CPUs are online
115 */
116
117void prom_cpus_done(void)
118{
119#ifdef CONFIG_MIPS_MT_SMTC
120
121#endif /* CONFIG_MIPS_MT_SMTC */
122}
123#endif /* CONFIG_MIPS32R2_MT_SMP */
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
new file mode 100644
index 000000000000..874a18e8ac24
--- /dev/null
+++ b/arch/mips/mipssim/sim_time.c
@@ -0,0 +1,200 @@
1#include <linux/types.h>
2#include <linux/init.h>
3#include <linux/kernel_stat.h>
4#include <linux/sched.h>
5#include <linux/spinlock.h>
6#include <linux/interrupt.h>
7#include <linux/mc146818rtc.h>
8#include <linux/mipsregs.h>
9#include <linux/smp.h>
10#include <linux/timex.h>
11
12#include <asm/hardirq.h>
13#include <asm/div64.h>
14#include <asm/cpu.h>
15#include <asm/time.h>
16#include <asm/irq.h>
17#include <asm/mc146818-time.h>
18#include <asm/msc01_ic.h>
19
20#include <asm/mips-boards/generic.h>
21#include <asm/mips-boards/prom.h>
22#include <asm/mips-boards/simint.h>
23
24
25unsigned long cpu_khz;
26
27irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
28{
29#ifdef CONFIG_SMP
30 int cpu = smp_processor_id();
31
32 /*
33 * CPU 0 handles the global timer interrupt job
34 * resets count/compare registers to trigger next timer int.
35 */
36#ifndef CONFIG_MIPS_MT_SMTC
37 if (cpu == 0) {
38 timer_interrupt(irq, dev_id);
39 } else {
40 /* Everyone else needs to reset the timer int here as
41 ll_local_timer_interrupt doesn't */
42 /*
43 * FIXME: need to cope with counter underflow.
44 * More support needs to be added to kernel/time for
45 * counter/timer interrupts on multiple CPU's
46 */
47 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
48 }
49#else /* SMTC */
50 /*
51 * In SMTC system, one Count/Compare set exists per VPE.
52 * Which TC within a VPE gets the interrupt is essentially
53 * random - we only know that it shouldn't be one with
54 * IXMT set. Whichever TC gets the interrupt needs to
55 * send special interprocessor interrupts to the other
56 * TCs to make sure that they schedule, etc.
57 *
58 * That code is specific to the SMTC kernel, not to
59 * the simulation platform, so it's invoked from
60 * the general MIPS timer_interrupt routine.
61 *
62 * We have a problem in that the interrupt vector code
63 * had to turn off the timer IM bit to avoid redundant
64 * entries, but we may never get to mips_cpu_irq_end
65 * to turn it back on again if the scheduler gets
66 * involved. So we clear the pending timer here,
67 * and re-enable the mask...
68 */
69
70 int vpflags = dvpe();
71 write_c0_compare (read_c0_count() - 1);
72 clear_c0_cause(0x100 << cp0_compare_irq);
73 set_c0_status(0x100 << cp0_compare_irq);
74 irq_enable_hazard();
75 evpe(vpflags);
76
77 if (cpu_data[cpu].vpe_id == 0)
78 timer_interrupt(irq, dev_id);
79 else
80 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
81 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
82
83#endif /* CONFIG_MIPS_MT_SMTC */
84
85 /*
86 * every CPU should do profiling and process accounting
87 */
88 local_timer_interrupt (irq, dev_id);
89
90 return IRQ_HANDLED;
91#else
92 return timer_interrupt (irq, dev_id);
93#endif
94}
95
96
97
98/*
99 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
100 */
101static unsigned int __init estimate_cpu_frequency(void)
102{
103 unsigned int prid = read_c0_prid() & 0xffff00;
104 unsigned int count;
105
106#if 1
107 /*
108 * hardwire the board frequency to 12MHz.
109 */
110
111 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
112 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
113 count = 12000000;
114 else
115 count = 6000000;
116#else
117 unsigned int flags;
118
119 local_irq_save(flags);
120
121 /* Start counter exactly on falling edge of update flag */
122 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
123 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
124
125 /* Start r4k counter. */
126 write_c0_count(0);
127
128 /* Read counter exactly on falling edge of update flag */
129 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
130 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
131
132 count = read_c0_count();
133
134 /* restore interrupts */
135 local_irq_restore(flags);
136#endif
137
138 mips_hpt_frequency = count;
139
140 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
141 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
142 count *= 2;
143
144 count += 5000; /* round */
145 count -= count%10000;
146
147 return count;
148}
149
150void __init sim_time_init(void)
151{
152 unsigned int est_freq, flags;
153
154 local_irq_save(flags);
155
156 /* Set Data mode - binary. */
157 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
158
159 est_freq = estimate_cpu_frequency ();
160
161 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
162 (est_freq % 1000000) * 100 / 1000000);
163
164 cpu_khz = est_freq / 1000;
165
166 local_irq_restore(flags);
167}
168
169static int mips_cpu_timer_irq;
170
171static void mips_timer_dispatch(void)
172{
173 do_IRQ(mips_cpu_timer_irq);
174}
175
176
177void __init plat_timer_setup(struct irqaction *irq)
178{
179 if (cpu_has_veic) {
180 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
181 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
182 } else {
183 if (cpu_has_vint)
184 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
185 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
186 }
187
188 /* we are using the cpu counter for timer interrupts */
189 irq->handler = sim_timer_interrupt;
190 setup_irq(mips_cpu_timer_irq, irq);
191
192#ifdef CONFIG_SMP
193 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
194 on seperate cpu's the first one tries to handle the second interrupt.
195 The effect is that the int remains disabled on the second cpu.
196 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
197 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
198 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
199#endif
200}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 02:32:41 -0500