10 files changed, 48 insertions, 48 deletions

diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 3c692abc2553..6fb29c3ff62d 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void)
 
 static inline int clz(unsigned long x)
 {
-        __asm__ (
+        __asm__(
         "       .set    push                                    \n"
         "       .set    mips32                                  \n"
         "       clz     %0, %1                                  \n"
@@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void)
                 spurious_interrupt();
 }
 
-static inline void init_atlas_irqs (int base)
+static inline void init_atlas_irqs(int base)
 {
         int i;
 
@@ -249,21 +249,21 @@ void __init arch_init_irq(void)
         case MIPS_REVISION_CORID_CORE_24K:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                 if (cpu_has_veic)
-                        init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE,
-                                       msc_eicirqmap, msc_nr_eicirqs);
+                        init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
+                                      msc_eicirqmap, msc_nr_eicirqs);
                 else
-                        init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE,
-                                       msc_irqmap, msc_nr_irqs);
+                        init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
+                                      msc_irqmap, msc_nr_irqs);
         }
 
         if (cpu_has_veic) {
-                set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
-                setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
+                set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
+                setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
         } else if (cpu_has_vint) {
-                set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
+                set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
-                setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
-                                &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
+                setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
+                               &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
 #else /* Not SMTC */
                 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
 #endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index 86bfc0548164..e405d112a067 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -55,7 +55,7 @@ void __init plat_mem_setup(void)
 
         ioport_resource.end = 0x7fffffff;
 
-        serial_init ();
+        serial_init();
 
 #ifdef CONFIG_KGDB
         kgdb_config();
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index e2c7147fedf7..30f1f54cb68b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -166,15 +166,15 @@ static void __init console_config(void)
                         bits = '8';
                 if (flow == '\0')
                         flow = 'r';
-                sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
-                strcat (prom_getcmdline(), console_string);
+                sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
+                strcat(prom_getcmdline(), console_string);
                 pr_info("Config serial console:%s\n", console_string);
         }
 }
 #endif
 
 #ifdef CONFIG_KGDB
-void __init kgdb_config (void)
+void __init kgdb_config(void)
 {
         extern int (*generic_putDebugChar)(char);
         extern char (*generic_getDebugChar)(void);
@@ -218,7 +218,7 @@ void __init kgdb_config (void)
                 {
                         char *s;
                         for (s = "Please connect GDB to this port\r\n"; *s; )
-                                generic_putDebugChar (*s++);
+                                generic_putDebugChar(*s++);
                 }
 
                 /* Breakpoint is invoked after interrupts are initialised */
@@ -226,7 +226,7 @@ void __init kgdb_config (void)
 }
 #endif
 
-void __init mips_nmi_setup (void)
+void __init mips_nmi_setup(void)
 {
         void *base;
         extern char except_vec_nmi;
@@ -238,7 +238,7 @@ void __init mips_nmi_setup (void)
         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 }
 
-void __init mips_ejtag_setup (void)
+void __init mips_ejtag_setup(void)
 {
         void *base;
         extern char except_vec_ejtag_debug;
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index ae39953da2c4..dc272c188233 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
         return &mdesc[0];
 }
 
-static int __init prom_memtype_classify (unsigned int type)
+static int __init prom_memtype_classify(unsigned int type)
 {
         switch (type) {
         case yamon_free:
@@ -158,7 +158,7 @@ void __init prom_meminit(void)
                 long type;
                 unsigned long base, size;
 
-                type = prom_memtype_classify (p->type);
+                type = prom_memtype_classify(p->type);
                 base = p->base;
                 size = p->size;
 
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index c9852206890a..b9743190609a 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -239,5 +239,5 @@ void __init mips_pcibios_init(void)
         iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
         ioport_resource.end = controller->io_resource->end;
 
-        register_pci_controller (controller);
+        register_pci_controller(controller);
 }
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 4fab3b2e8736..1d00b778ff1e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -134,7 +134,7 @@ void __init plat_time_init(void)
         /* Set Data mode - binary. */
         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 
-        est_freq = estimate_cpu_frequency ();
+        est_freq = estimate_cpu_frequency();
 
         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
                (est_freq%1000000)*100/1000000);
@@ -166,7 +166,7 @@ void __init plat_perf_setup(void)
 
 #ifdef MSC01E_INT_BASE
         if (cpu_has_veic) {
-                set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
+                set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
                 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
         } else
 #endif
@@ -183,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
 {
 #ifdef MSC01E_INT_BASE
         if (cpu_has_veic) {
-                set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
+                set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
         }
         else
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5e..8232392750a8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
 
 static inline int clz(unsigned long x)
 {
-        __asm__ (
+        __asm__(
         "       .set    push                                    \n"
         "       .set    mips32                                  \n"
         "       clz     %0, %1                                  \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
         case MIPS_REVISION_SCON_SOCIT:
         case MIPS_REVISION_SCON_ROCIT:
                 if (cpu_has_veic)
-                        init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+                        init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
                 else
-                        init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+                        init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
                 break;
 
         case MIPS_REVISION_SCON_SOCITSC:
         case MIPS_REVISION_SCON_SOCITSCP:
                 if (cpu_has_veic)
-                        init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+                        init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
                 else
-                        init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+                        init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
         }
 
         if (cpu_has_veic) {
-                set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
-                set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
-                setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
-                setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
+                set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
+                set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
+                setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
+                setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
         }
         else if (cpu_has_vint) {
-                set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
-                set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
+                set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
+                set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
-                setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
+                setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
                         (0x100 << MIPSCPU_INT_I8259A));
-                setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
+                setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
                 /*
                  * Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
                                 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
                 }
 #else /* Not SMTC */
-                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 #endif /* CONFIG_MIPS_MT_SMTC */
         }
         else {
-                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
         }
 }
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index a5a5a43a1984..e243d5efcb38 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -99,7 +99,7 @@ void __init plat_mem_setup(void)
         enable_dma(4);
 
 #ifdef CONFIG_KGDB
-        kgdb_config ();
+        kgdb_config();
 #endif
 
         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -108,7 +108,7 @@ void __init plat_mem_setup(void)
                 argptr = prom_getcmdline();
                 if (strstr(argptr, "debug")) {
                         BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
-                        printk ("Enabled Bonito debug mode\n");
+                        printk("Enabled Bonito debug mode\n");
                 }
                 else
                         BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -159,14 +159,14 @@ void __init plat_mem_setup(void)
                 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
                         printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
                         argptr += strlen(argptr);
-                        sprintf (argptr, " idebus=%d", pciclock);
+                        sprintf(argptr, " idebus=%d", pciclock);
                         if (pciclock < 20 || pciclock > 66)
-                                printk ("WARNING: IDE timing calculations will be incorrect\n");
+                                printk("WARNING: IDE timing calculations will be incorrect\n");
                 }
         }
 #endif
 #ifdef CONFIG_BLK_DEV_FD
-        fd_activate ();
+        fd_activate();
 #endif
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9ca0f82f1360..ec6dd194c14a 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -31,7 +31,7 @@
 
 static inline int clz(unsigned long x)
 {
-        __asm__ (
+        __asm__(
         "       .set    push                                    \n"
         "       .set    mips32                                  \n"
         "       clz     %0, %1                                  \n"
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index fad58972f3ac..1fb61b852304 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -49,7 +49,7 @@ void __init plat_mem_setup(void)
 {
         ioport_resource.end = 0x7fffffff;
 
-        serial_init ();
+        serial_init();
 
         mips_reboot_setup();
 }