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-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c6
-rw-r--r--arch/mips/mips-boards/generic/init.c8
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c129
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c210
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c68
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c2
6 files changed, 241 insertions, 182 deletions
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index e405d112a067..5c500802271e 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -34,12 +34,6 @@
34#include <asm/time.h> 34#include <asm/time.h>
35#include <asm/traps.h> 35#include <asm/traps.h>
36 36
37extern void mips_reboot_setup(void);
38
39#ifdef CONFIG_KGDB
40extern void kgdb_config(void);
41#endif
42
43static void __init serial_init(void); 37static void __init serial_init(void);
44 38
45const char *get_system_type(void) 39const char *get_system_type(void)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 30f1f54cb68b..1695dca5506b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -250,6 +250,8 @@ void __init mips_ejtag_setup(void)
250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
251} 251}
252 252
253extern struct plat_smp_ops msmtc_smp_ops;
254
253void __init prom_init(void) 255void __init prom_init(void)
254{ 256{
255 prom_argc = fw_arg0; 257 prom_argc = fw_arg0;
@@ -416,4 +418,10 @@ void __init prom_init(void)
416#ifdef CONFIG_SERIAL_8250_CONSOLE 418#ifdef CONFIG_SERIAL_8250_CONSOLE
417 console_config(); 419 console_config();
418#endif 420#endif
421#ifdef CONFIG_MIPS_MT_SMP
422 register_smp_ops(&vsmp_smp_ops);
423#endif
424#ifdef CONFIG_MIPS_MT_SMTC
425 register_smp_ops(&msmtc_smp_ops);
426#endif
419} 427}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index f010261b75d8..dbe60eb55e29 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -26,13 +26,13 @@
26#include <linux/sched.h> 26#include <linux/sched.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/io.h>
29#include <linux/kernel_stat.h> 30#include <linux/kernel_stat.h>
30#include <linux/kernel.h> 31#include <linux/kernel.h>
31#include <linux/random.h> 32#include <linux/random.h>
32 33
33#include <asm/i8259.h> 34#include <asm/i8259.h>
34#include <asm/irq_cpu.h> 35#include <asm/irq_cpu.h>
35#include <asm/io.h>
36#include <asm/irq_regs.h> 36#include <asm/irq_regs.h>
37#include <asm/mips-boards/malta.h> 37#include <asm/mips-boards/malta.h>
38#include <asm/mips-boards/maltaint.h> 38#include <asm/mips-boards/maltaint.h>
@@ -47,7 +47,7 @@ static DEFINE_SPINLOCK(mips_irq_lock);
47static inline int mips_pcibios_iack(void) 47static inline int mips_pcibios_iack(void)
48{ 48{
49 int irq; 49 int irq;
50 u32 dummy; 50 u32 dummy;
51 51
52 /* 52 /*
53 * Determine highest priority pending interrupt by performing 53 * Determine highest priority pending interrupt by performing
@@ -58,7 +58,7 @@ static inline int mips_pcibios_iack(void)
58 case MIPS_REVISION_SCON_ROCIT: 58 case MIPS_REVISION_SCON_ROCIT:
59 case MIPS_REVISION_SCON_SOCITSC: 59 case MIPS_REVISION_SCON_SOCITSC:
60 case MIPS_REVISION_SCON_SOCITSCP: 60 case MIPS_REVISION_SCON_SOCITSCP:
61 MSC_READ(MSC01_PCI_IACK, irq); 61 MSC_READ(MSC01_PCI_IACK, irq);
62 irq &= 0xff; 62 irq &= 0xff;
63 break; 63 break;
64 case MIPS_REVISION_SCON_GT64120: 64 case MIPS_REVISION_SCON_GT64120:
@@ -83,7 +83,7 @@ static inline int mips_pcibios_iack(void)
83 BONITO_PCIMAP_CFG = 0; 83 BONITO_PCIMAP_CFG = 0;
84 break; 84 break;
85 default: 85 default:
86 printk("Unknown system controller.\n"); 86 printk(KERN_WARNING "Unknown system controller.\n");
87 return -1; 87 return -1;
88 } 88 }
89 return irq; 89 return irq;
@@ -114,7 +114,8 @@ static void malta_hw0_irqdispatch(void)
114 114
115 irq = get_int(); 115 irq = get_int();
116 if (irq < 0) { 116 if (irq < 0) {
117 return; /* interrupt has already been cleared */ 117 /* interrupt has already been cleared */
118 return;
118 } 119 }
119 120
120 do_IRQ(MALTA_INT_BASE + irq); 121 do_IRQ(MALTA_INT_BASE + irq);
@@ -123,15 +124,15 @@ static void malta_hw0_irqdispatch(void)
123static void corehi_irqdispatch(void) 124static void corehi_irqdispatch(void)
124{ 125{
125 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 126 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
126 unsigned int pcimstat, intisr, inten, intpol; 127 unsigned int pcimstat, intisr, inten, intpol;
127 unsigned int intrcause, datalo, datahi; 128 unsigned int intrcause, datalo, datahi;
128 struct pt_regs *regs = get_irq_regs(); 129 struct pt_regs *regs = get_irq_regs();
129 130
130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 131 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
131 printk("epc : %08lx\nStatus: %08lx\n" 132 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
132 "Cause : %08lx\nbadVaddr : %08lx\n", 133 "Cause : %08lx\nbadVaddr : %08lx\n",
133 regs->cp0_epc, regs->cp0_status, 134 regs->cp0_epc, regs->cp0_status,
134 regs->cp0_cause, regs->cp0_badvaddr); 135 regs->cp0_cause, regs->cp0_badvaddr);
135 136
136 /* Read all the registers and then print them as there is a 137 /* Read all the registers and then print them as there is a
137 problem with interspersed printk's upsetting the Bonito controller. 138 problem with interspersed printk's upsetting the Bonito controller.
@@ -139,41 +140,41 @@ static void corehi_irqdispatch(void)
139 */ 140 */
140 141
141 switch (mips_revision_sconid) { 142 switch (mips_revision_sconid) {
142 case MIPS_REVISION_SCON_SOCIT: 143 case MIPS_REVISION_SCON_SOCIT:
143 case MIPS_REVISION_SCON_ROCIT: 144 case MIPS_REVISION_SCON_ROCIT:
144 case MIPS_REVISION_SCON_SOCITSC: 145 case MIPS_REVISION_SCON_SOCITSC:
145 case MIPS_REVISION_SCON_SOCITSCP: 146 case MIPS_REVISION_SCON_SOCITSCP:
146 ll_msc_irq(); 147 ll_msc_irq();
147 break; 148 break;
148 case MIPS_REVISION_SCON_GT64120: 149 case MIPS_REVISION_SCON_GT64120:
149 intrcause = GT_READ(GT_INTRCAUSE_OFS); 150 intrcause = GT_READ(GT_INTRCAUSE_OFS);
150 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 151 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
151 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 152 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
152 printk("GT_INTRCAUSE = %08x\n", intrcause); 153 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
153 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); 154 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
154 break; 155 datahi, datalo);
155 case MIPS_REVISION_SCON_BONITO: 156 break;
156 pcibadaddr = BONITO_PCIBADADDR; 157 case MIPS_REVISION_SCON_BONITO:
157 pcimstat = BONITO_PCIMSTAT; 158 pcibadaddr = BONITO_PCIBADADDR;
158 intisr = BONITO_INTISR; 159 pcimstat = BONITO_PCIMSTAT;
159 inten = BONITO_INTEN; 160 intisr = BONITO_INTISR;
160 intpol = BONITO_INTPOL; 161 inten = BONITO_INTEN;
161 intedge = BONITO_INTEDGE; 162 intpol = BONITO_INTPOL;
162 intsteer = BONITO_INTSTEER; 163 intedge = BONITO_INTEDGE;
163 pcicmd = BONITO_PCICMD; 164 intsteer = BONITO_INTSTEER;
164 printk("BONITO_INTISR = %08x\n", intisr); 165 pcicmd = BONITO_PCICMD;
165 printk("BONITO_INTEN = %08x\n", inten); 166 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
166 printk("BONITO_INTPOL = %08x\n", intpol); 167 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
167 printk("BONITO_INTEDGE = %08x\n", intedge); 168 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
168 printk("BONITO_INTSTEER = %08x\n", intsteer); 169 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
169 printk("BONITO_PCICMD = %08x\n", pcicmd); 170 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
170 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); 171 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
171 printk("BONITO_PCIMSTAT = %08x\n", pcimstat); 172 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
172 break; 173 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
173 } 174 break;
174 175 }
175 /* We die here*/ 176
176 die("CoreHi interrupt", regs); 177 die("CoreHi interrupt", regs);
177} 178}
178 179
179static inline int clz(unsigned long x) 180static inline int clz(unsigned long x)
@@ -214,9 +215,9 @@ static inline unsigned int irq_ffs(unsigned int pending)
214 215
215 t0 = pending & 0x8000; 216 t0 = pending & 0x8000;
216 t0 = t0 < 1; 217 t0 = t0 < 1;
217 //t0 = t0 << 2; 218 /* t0 = t0 << 2; */
218 a0 = a0 - t0; 219 a0 = a0 - t0;
219 //pending = pending << t0; 220 /* pending = pending << t0; */
220 221
221 return a0; 222 return a0;
222#endif 223#endif
@@ -299,21 +300,29 @@ void __init arch_init_irq(void)
299 if (!cpu_has_veic) 300 if (!cpu_has_veic)
300 mips_cpu_irq_init(); 301 mips_cpu_irq_init();
301 302
302 switch(mips_revision_sconid) { 303 switch (mips_revision_sconid) {
303 case MIPS_REVISION_SCON_SOCIT: 304 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 305 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 306 if (cpu_has_veic)
306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 307 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
308 MSC01E_INT_BASE, msc_eicirqmap,
309 msc_nr_eicirqs);
307 else 310 else
308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 311 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
312 MSC01C_INT_BASE, msc_irqmap,
313 msc_nr_irqs);
309 break; 314 break;
310 315
311 case MIPS_REVISION_SCON_SOCITSC: 316 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 317 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 318 if (cpu_has_veic)
314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 319 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
320 MSC01E_INT_BASE, msc_eicirqmap,
321 msc_nr_eicirqs);
315 else 322 else
316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 323 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
324 MSC01C_INT_BASE, msc_irqmap,
325 msc_nr_irqs);
317 } 326 }
318 327
319 if (cpu_has_veic) { 328 if (cpu_has_veic) {
@@ -321,8 +330,7 @@ void __init arch_init_irq(void)
321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 330 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 331 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 332 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 333 } else if (cpu_has_vint) {
325 else if (cpu_has_vint) {
326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 334 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 335 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 336#ifdef CONFIG_MIPS_MT_SMTC
@@ -344,11 +352,12 @@ void __init arch_init_irq(void)
344 } 352 }
345#else /* Not SMTC */ 353#else /* Not SMTC */
346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 354 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 355 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
356 &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 357#endif /* CONFIG_MIPS_MT_SMTC */
349 } 358 } else {
350 else {
351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 359 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 360 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
361 &corehi_irqaction);
353 } 362 }
354} 363}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index bc43a5c2224d..2cd8f5734b36 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) Dmitri Vorobiev
4 * 5 *
5 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -15,39 +16,57 @@
15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 */ 18 */
19#include <linux/cpu.h>
18#include <linux/init.h> 20#include <linux/init.h>
19#include <linux/sched.h> 21#include <linux/sched.h>
20#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/irq.h>
21#include <linux/pci.h> 24#include <linux/pci.h>
22#include <linux/screen_info.h> 25#include <linux/screen_info.h>
26#include <linux/time.h>
23 27
24#include <asm/cpu.h>
25#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
26#include <asm/irq.h>
27#include <asm/mips-boards/generic.h> 29#include <asm/mips-boards/generic.h>
28#include <asm/mips-boards/prom.h> 30#include <asm/mips-boards/prom.h>
29#include <asm/mips-boards/malta.h> 31#include <asm/mips-boards/malta.h>
30#include <asm/mips-boards/maltaint.h> 32#include <asm/mips-boards/maltaint.h>
31#include <asm/dma.h> 33#include <asm/dma.h>
32#include <asm/time.h>
33#include <asm/traps.h> 34#include <asm/traps.h>
34#ifdef CONFIG_VT 35#ifdef CONFIG_VT
35#include <linux/console.h> 36#include <linux/console.h>
36#endif 37#endif
37 38
38extern void mips_reboot_setup(void);
39extern unsigned long mips_rtc_get_time(void);
40
41#ifdef CONFIG_KGDB
42extern void kgdb_config(void);
43#endif
44
45struct resource standard_io_resources[] = { 39struct resource standard_io_resources[] = {
46 { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY }, 40 {
47 { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY }, 41 .name = "dma1",
48 { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY }, 42 .start = 0x00,
49 { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY }, 43 .end = 0x1f,
50 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, 44 .flags = IORESOURCE_BUSY
45 },
46 {
47 .name = "timer",
48 .start = 0x40,
49 .end = 0x5f,
50 .flags = IORESOURCE_BUSY
51 },
52 {
53 .name = "keyboard",
54 .start = 0x60,
55 .end = 0x6f,
56 .flags = IORESOURCE_BUSY
57 },
58 {
59 .name = "dma page reg",
60 .start = 0x80,
61 .end = 0x8f,
62 .flags = IORESOURCE_BUSY
63 },
64 {
65 .name = "dma2",
66 .start = 0xc0,
67 .end = 0xdf,
68 .flags = IORESOURCE_BUSY
69 },
51}; 70};
52 71
53const char *get_system_type(void) 72const char *get_system_type(void)
@@ -62,7 +81,7 @@ const char display_string[] = " LINUX ON MALTA ";
62#endif /* CONFIG_MIPS_MT_SMTC */ 81#endif /* CONFIG_MIPS_MT_SMTC */
63 82
64#ifdef CONFIG_BLK_DEV_FD 83#ifdef CONFIG_BLK_DEV_FD
65void __init fd_activate(void) 84static void __init fd_activate(void)
66{ 85{
67 /* 86 /*
68 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 87 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
@@ -83,6 +102,85 @@ void __init fd_activate(void)
83} 102}
84#endif 103#endif
85 104
105#ifdef CONFIG_BLK_DEV_IDE
106static void __init pci_clock_check(void)
107{
108 unsigned int __iomem *jmpr_p =
109 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
110 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
111 static const int pciclocks[] __initdata = {
112 33, 20, 25, 30, 12, 16, 37, 10
113 };
114 int pciclock = pciclocks[jmpr];
115 char *argptr = prom_getcmdline();
116
117 if (pciclock != 33 && !strstr(argptr, "idebus=")) {
118 printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
119 "setting idebus\n", pciclock);
120 argptr += strlen(argptr);
121 sprintf(argptr, " idebus=%d", pciclock);
122 if (pciclock < 20 || pciclock > 66)
123 printk(KERN_WARNING "WARNING: IDE timing "
124 "calculations will be incorrect\n");
125 }
126}
127#endif
128
129#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
130static void __init screen_info_setup(void)
131{
132 screen_info = (struct screen_info) {
133 .orig_x = 0,
134 .orig_y = 25,
135 .ext_mem_k = 0,
136 .orig_video_page = 0,
137 .orig_video_mode = 0,
138 .orig_video_cols = 80,
139 .unused2 = 0,
140 .orig_video_ega_bx = 0,
141 .unused3 = 0,
142 .orig_video_lines = 25,
143 .orig_video_isVGA = VIDEO_TYPE_VGAC,
144 .orig_video_points = 16
145 };
146}
147#endif
148
149static void __init bonito_quirks_setup(void)
150{
151 char *argptr;
152
153 argptr = prom_getcmdline();
154 if (strstr(argptr, "debug")) {
155 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
156 printk(KERN_INFO "Enabled Bonito debug mode\n");
157 } else
158 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
159
160#ifdef CONFIG_DMA_COHERENT
161 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
162 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
163 printk(KERN_INFO "Enabled Bonito CPU coherency\n");
164
165 argptr = prom_getcmdline();
166 if (strstr(argptr, "iobcuncached")) {
167 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
168 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
169 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
170 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
171 printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
172 } else {
173 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
174 BONITO_PCIMEMBASECFG |=
175 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
176 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
177 printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
178 }
179 } else
180 panic("Hardware DMA cache coherency not supported");
181#endif
182}
183
86void __init plat_mem_setup(void) 184void __init plat_mem_setup(void)
87{ 185{
88 unsigned int i; 186 unsigned int i;
@@ -102,86 +200,24 @@ void __init plat_mem_setup(void)
102 kgdb_config(); 200 kgdb_config();
103#endif 201#endif
104 202
105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
106 char *argptr;
107
108 argptr = prom_getcmdline();
109 if (strstr(argptr, "debug")) {
110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
111 printk("Enabled Bonito debug mode\n");
112 }
113 else
114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
115
116#ifdef CONFIG_DMA_COHERENT
117 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
118 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
119 printk("Enabled Bonito CPU coherency\n");
120
121 argptr = prom_getcmdline();
122 if (strstr(argptr, "iobcuncached")) {
123 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
124 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
125 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
126 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
127 printk("Disabled Bonito IOBC coherency\n");
128 }
129 else {
130 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
131 BONITO_PCIMEMBASECFG |=
132 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
133 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
134 printk("Enabled Bonito IOBC coherency\n");
135 }
136 }
137 else
138 panic("Hardware DMA cache coherency not supported");
139
140#endif
141 }
142#ifdef CONFIG_DMA_COHERENT 203#ifdef CONFIG_DMA_COHERENT
143 else { 204 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
144 panic("Hardware DMA cache coherency not supported"); 205 panic("Hardware DMA cache coherency not supported");
145 }
146#endif 206#endif
147 207
208 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
209 bonito_quirks_setup();
210
148#ifdef CONFIG_BLK_DEV_IDE 211#ifdef CONFIG_BLK_DEV_IDE
149 /* Check PCI clock */ 212 pci_clock_check();
150 {
151 unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
152 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
153 static const int pciclocks[] __initdata = {
154 33, 20, 25, 30, 12, 16, 37, 10
155 };
156 int pciclock = pciclocks[jmpr];
157 char *argptr = prom_getcmdline();
158
159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
161 argptr += strlen(argptr);
162 sprintf(argptr, " idebus=%d", pciclock);
163 if (pciclock < 20 || pciclock > 66)
164 printk("WARNING: IDE timing calculations will be incorrect\n");
165 }
166 }
167#endif 213#endif
214
168#ifdef CONFIG_BLK_DEV_FD 215#ifdef CONFIG_BLK_DEV_FD
169 fd_activate(); 216 fd_activate();
170#endif 217#endif
171#ifdef CONFIG_VT 218
172#if defined(CONFIG_VGA_CONSOLE) 219#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
173 screen_info = (struct screen_info) { 220 screen_info_setup();
174 0, 25, /* orig-x, orig-y */
175 0, /* unused */
176 0, /* orig-video-page */
177 0, /* orig-video-mode */
178 80, /* orig-video-cols */
179 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
180 25, /* orig-video-lines */
181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
182 16 /* orig-video-points */
183 };
184#endif
185#endif 221#endif
186 mips_reboot_setup(); 222 mips_reboot_setup();
187} 223}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index 5c980f4a48fe..5ea705e49454 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -15,28 +15,26 @@
15 * Cause the specified action to be performed on a targeted "CPU" 15 * Cause the specified action to be performed on a targeted "CPU"
16 */ 16 */
17 17
18void core_send_ipi(int cpu, unsigned int action) 18static void msmtc_send_ipi_single(int cpu, unsigned int action)
19{ 19{
20 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ 20 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
21 smtc_send_ipi(cpu, LINUX_SMP_IPI, action); 21 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
22} 22}
23 23
24/* 24static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
25 * Platform "CPU" startup hook
26 */
27
28void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
29{ 25{
30 smtc_boot_secondary(cpu, idle); 26 unsigned int i;
27
28 for_each_cpu_mask(i, mask)
29 msmtc_send_ipi_single(i, action);
31} 30}
32 31
33/* 32/*
34 * Post-config but pre-boot cleanup entry point 33 * Post-config but pre-boot cleanup entry point
35 */ 34 */
36 35static void __cpuinit msmtc_init_secondary(void)
37void __cpuinit prom_init_secondary(void)
38{ 36{
39 void smtc_init_secondary(void); 37 void smtc_init_secondary(void);
40 int myvpe; 38 int myvpe;
41 39
42 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ 40 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
@@ -50,45 +48,61 @@ void __cpuinit prom_init_secondary(void)
50 set_c0_status(0x100 << cp0_perfcount_irq); 48 set_c0_status(0x100 << cp0_perfcount_irq);
51 } 49 }
52 50
53 smtc_init_secondary(); 51 smtc_init_secondary();
54} 52}
55 53
56/* 54/*
57 * Platform SMP pre-initialization 55 * Platform "CPU" startup hook
58 *
59 * As noted above, we can assume a single CPU for now
60 * but it may be multithreaded.
61 */ 56 */
62 57static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle)
63void __cpuinit plat_smp_setup(void)
64{ 58{
65 if (read_c0_config3() & (1<<2)) 59 smtc_boot_secondary(cpu, idle);
66 mipsmt_build_cpu_map(0);
67} 60}
68 61
69void __init plat_prepare_cpus(unsigned int max_cpus) 62/*
63 * SMP initialization finalization entry point
64 */
65static void __cpuinit msmtc_smp_finish(void)
70{ 66{
71 if (read_c0_config3() & (1<<2)) 67 smtc_smp_finish();
72 mipsmt_prepare_cpus();
73} 68}
74 69
75/* 70/*
76 * SMP initialization finalization entry point 71 * Hook for after all CPUs are online
77 */ 72 */
78 73
79void __cpuinit prom_smp_finish(void) 74static void msmtc_cpus_done(void)
80{ 75{
81 smtc_smp_finish();
82} 76}
83 77
84/* 78/*
85 * Hook for after all CPUs are online 79 * Platform SMP pre-initialization
80 *
81 * As noted above, we can assume a single CPU for now
82 * but it may be multithreaded.
86 */ 83 */
87 84
88void prom_cpus_done(void) 85static void __init msmtc_smp_setup(void)
89{ 86{
87 mipsmt_build_cpu_map(0);
90} 88}
91 89
90static void __init msmtc_prepare_cpus(unsigned int max_cpus)
91{
92 mipsmt_prepare_cpus();
93}
94
95struct plat_smp_ops msmtc_smp_ops = {
96 .send_ipi_single = msmtc_send_ipi_single,
97 .send_ipi_mask = msmtc_send_ipi_mask,
98 .init_secondary = msmtc_init_secondary,
99 .smp_finish = msmtc_smp_finish,
100 .cpus_done = msmtc_cpus_done,
101 .boot_secondary = msmtc_boot_secondary,
102 .smp_setup = msmtc_smp_setup,
103 .prepare_cpus = msmtc_prepare_cpus,
104};
105
92#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 106#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
93/* 107/*
94 * IRQ affinity hook 108 * IRQ affinity hook
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 1fb61b852304..8aa8e5b7b074 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -34,8 +34,6 @@
34#include <asm/mips-boards/seadint.h> 34#include <asm/mips-boards/seadint.h>
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37extern void mips_reboot_setup(void);
38
39static void __init serial_init(void); 37static void __init serial_init(void);
40 38
41const char *get_system_type(void) 39const char *get_system_type(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 06:14:01 -0500