1 files changed, 0 insertions, 100 deletions
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
deleted file mode 100644
index b7444e74a6a1..000000000000
--- a/arch/mips/mips-boards/sim/sim_irq.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (C) 1999, 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Interrupt exception dispatch code.
- *
- */
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-#include <asm/mips-boards/simint.h>
-        .text
-        .set    noreorder
-        .set    noat
-        .align  5
-        NESTED(simIRQ, PT_SIZE, sp)
-        SAVE_ALL
-        CLI
-        .set    at
-        mfc0    s0, CP0_CAUSE           # get irq bits
-        mfc0    s1, CP0_STATUS          # get irq mask
-        andi    s0, ST0_IM              # CAUSE.CE may be non-zero!
-        and     s0, s1
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-        .set    mips32
-        clz     a0, s0
-        .set    mips0
-        negu    a0
-        addu    a0, 31-CAUSEB_IP
-        bltz    a0, spurious
-#else
-        beqz    s0, spurious
-         li     a0, 7
-        and     t0, s0, 0xf000
-        sltiu   t0, t0, 1
-        sll     t0, 2
-        subu    a0, t0
-        sll     s0, t0
-        and     t0, s0, 0xc000
-        sltiu   t0, t0, 1
-        sll     t0, 1
-        subu    a0, t0
-        sll     s0, t0
-        and     t0, s0, 0x8000
-        sltiu   t0, t0, 1
-        # sll   t0, 0
-        subu    a0, t0
-        # sll   s0, t0
-#endif
-#ifdef CASCADE_IRQ
-         li     a1, CASCADE_IRQ
-        bne     a0, a1, 1f
-         addu   a0, MIPSCPU_INT_BASE
-        jal     CASCADE_DISPATCH
-         move    a0, sp
-        j       ret_from_irq
-         nop
-1:
-#else
-         addu   a0, MIPSCPU_INT_BASE
-#endif
-        jal     do_IRQ
-         move   a1, sp
-        j       ret_from_irq
-         nop
-spurious:
-        jal     spurious_interrupt
-         nop
-        j       ret_from_irq
-         nop
-        END(simIRQ)

diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S deleted file mode 100644 index b7444e74a6a1..000000000000 --- a/arch/mips/mips-boards/sim/sim_irq.S +++ /dev/null
@@ -1,100 +0,0 @@
1	/*
2	* Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3	*
4	* This program is free software; you can distribute it and/or modify it
5	* under the terms of the GNU General Public License (Version 2) as
6	* published by the Free Software Foundation.
7	*
8	* This program is distributed in the hope it will be useful, but WITHOUT
9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11	* for more details.
12	*
13	* You should have received a copy of the GNU General Public License along
14	* with this program; if not, write to the Free Software Foundation, Inc.,
15	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16	*
17	* Interrupt exception dispatch code.
18	*
19	*/
20
21	#include <asm/asm.h>
22	#include <asm/mipsregs.h>
23	#include <asm/regdef.h>
24	#include <asm/stackframe.h>
25
26	#include <asm/mips-boards/simint.h>
27
28
29	.text
30	.set noreorder
31	.set noat
32	.align 5
33	NESTED(simIRQ, PT_SIZE, sp)
34	SAVE_ALL
35	CLI
36	.set at
37
38	mfc0 s0, CP0_CAUSE # get irq bits
39	mfc0 s1, CP0_STATUS # get irq mask
40	andi s0, ST0_IM # CAUSE.CE may be non-zero!
41	and s0, s1
42
43	#if defined(CONFIG_CPU_MIPS32) \|\| defined(CONFIG_CPU_MIPS64)
44	.set mips32
45	clz a0, s0
46	.set mips0
47	negu a0
48	addu a0, 31-CAUSEB_IP
49	bltz a0, spurious
50	#else
51	beqz s0, spurious
52	li a0, 7
53
54	and t0, s0, 0xf000
55	sltiu t0, t0, 1
56	sll t0, 2
57	subu a0, t0
58	sll s0, t0
59
60	and t0, s0, 0xc000
61	sltiu t0, t0, 1
62	sll t0, 1
63	subu a0, t0
64	sll s0, t0
65
66	and t0, s0, 0x8000
67	sltiu t0, t0, 1
68	# sll t0, 0
69	subu a0, t0
70	# sll s0, t0
71	#endif
72
73	#ifdef CASCADE_IRQ
74	li a1, CASCADE_IRQ
75	bne a0, a1, 1f
76	addu a0, MIPSCPU_INT_BASE
77
78	jal CASCADE_DISPATCH
79	move a0, sp
80
81	j ret_from_irq
82	nop
83	1:
84	#else
85	addu a0, MIPSCPU_INT_BASE
86	#endif
87
88	jal do_IRQ
89	move a1, sp
90
91	j ret_from_irq
92	nop
93
94
95	spurious:
96	jal spurious_interrupt
97	nop
98	j ret_from_irq
99	nop
100	END(simIRQ)