diff options
Diffstat (limited to 'arch/mips/mips-boards/sim/sim_IRQ.c')
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_IRQ.c | 147 |
1 files changed, 0 insertions, 147 deletions
diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c deleted file mode 100644 index ec549f3e2011..000000000000 --- a/arch/mips/mips-boards/sim/sim_IRQ.c +++ /dev/null | |||
| @@ -1,147 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Carsten Langgaard, carstenl@mips.com | ||
| 3 | * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can distribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License (Version 2) as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 12 | * for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
| 17 | * | ||
| 18 | * Interrupt exception dispatch code. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <asm/asm.h> | ||
| 22 | #include <asm/mipsregs.h> | ||
| 23 | #include <asm/regdef.h> | ||
| 24 | #include <asm/stackframe.h> | ||
| 25 | |||
| 26 | /* A lot of complication here is taken away because: | ||
| 27 | * | ||
| 28 | * 1) We handle one interrupt and return, sitting in a loop and moving across | ||
| 29 | * all the pending IRQ bits in the cause register is _NOT_ the answer, the | ||
| 30 | * common case is one pending IRQ so optimize in that direction. | ||
| 31 | * | ||
| 32 | * 2) We need not check against bits in the status register IRQ mask, that | ||
| 33 | * would make this routine slow as hell. | ||
| 34 | * | ||
| 35 | * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in | ||
| 36 | * between like BSD spl() brain-damage. | ||
| 37 | * | ||
| 38 | * Furthermore, the IRQs on the MIPS board look basically (barring software | ||
| 39 | * IRQs which we don't use at all and all external interrupt sources are | ||
| 40 | * combined together on hardware interrupt 0 (MIPS IRQ 2)) like: | ||
| 41 | * | ||
| 42 | * MIPS IRQ Source | ||
| 43 | * -------- ------ | ||
| 44 | * 0 Software (ignored) | ||
| 45 | * 1 Software (ignored) | ||
| 46 | * 2 Combined hardware interrupt (hw0) | ||
| 47 | * 3 Hardware (ignored) | ||
| 48 | * 4 Hardware (ignored) | ||
| 49 | * 5 Hardware (ignored) | ||
| 50 | * 6 Hardware (ignored) | ||
| 51 | * 7 R4k timer (what we use) | ||
| 52 | * | ||
| 53 | * Note: On the SEAD board thing are a little bit different. | ||
| 54 | * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired | ||
| 55 | * wired to UART1. | ||
| 56 | * | ||
| 57 | * We handle the IRQ according to _our_ priority which is: | ||
| 58 | * | ||
| 59 | * Highest ---- R4k Timer | ||
| 60 | * Lowest ---- Combined hardware interrupt | ||
| 61 | * | ||
| 62 | * then we just return, if multiple IRQs are pending then we will just take | ||
| 63 | * another exception, big deal. | ||
| 64 | */ | ||
| 65 | |||
| 66 | .text | ||
| 67 | .set noreorder | ||
| 68 | .set noat | ||
| 69 | .align 5 | ||
| 70 | NESTED(mipsIRQ, PT_SIZE, sp) | ||
| 71 | SAVE_ALL | ||
| 72 | CLI | ||
| 73 | .set at | ||
| 74 | |||
| 75 | mfc0 s0, CP0_CAUSE # get irq bits | ||
| 76 | mfc0 s1, CP0_STATUS # get irq mask | ||
| 77 | and s0, s1 | ||
| 78 | |||
| 79 | /* First we check for r4k counter/timer IRQ. */ | ||
| 80 | andi a0, s0, CAUSEF_IP7 | ||
| 81 | beq a0, zero, 1f | ||
| 82 | andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt | ||
| 83 | |||
| 84 | /* Wheee, a timer interrupt. */ | ||
| 85 | move a0, sp | ||
| 86 | jal mips_timer_interrupt | ||
| 87 | nop | ||
| 88 | |||
| 89 | j ret_from_irq | ||
| 90 | nop | ||
| 91 | |||
| 92 | 1: | ||
| 93 | #if defined(CONFIG_MIPS_SEAD) | ||
| 94 | beq a0, zero, 1f | ||
| 95 | andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt | ||
| 96 | #else | ||
| 97 | beq a0, zero, 1f # delay slot, check hw3 interrupt | ||
| 98 | andi a0, s0, CAUSEF_IP5 | ||
| 99 | #endif | ||
| 100 | |||
| 101 | /* Wheee, combined hardware level zero interrupt. */ | ||
| 102 | #if defined(CONFIG_MIPS_ATLAS) | ||
| 103 | jal atlas_hw0_irqdispatch | ||
| 104 | #elif defined(CONFIG_MIPS_MALTA) | ||
| 105 | jal malta_hw0_irqdispatch | ||
| 106 | #elif defined(CONFIG_MIPS_SEAD) | ||
| 107 | jal sead_hw0_irqdispatch | ||
| 108 | #else | ||
| 109 | #error "MIPS board not supported\n" | ||
| 110 | #endif | ||
| 111 | move a0, sp # delay slot | ||
| 112 | |||
| 113 | j ret_from_irq | ||
| 114 | nop # delay slot | ||
| 115 | |||
| 116 | 1: | ||
| 117 | #if defined(CONFIG_MIPS_SEAD) | ||
| 118 | beq a0, zero, 1f | ||
| 119 | andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt | ||
| 120 | jal sead_hw1_irqdispatch | ||
| 121 | move a0, sp # delay slot | ||
| 122 | j ret_from_irq | ||
| 123 | nop # delay slot | ||
| 124 | 1: | ||
| 125 | #endif | ||
| 126 | #if defined(CONFIG_MIPS_MALTA) | ||
| 127 | beq a0, zero, 1f # check hw3 (coreHI) interrupt | ||
| 128 | nop | ||
| 129 | jal corehi_irqdispatch | ||
| 130 | move a0, sp | ||
| 131 | j ret_from_irq | ||
| 132 | nop | ||
| 133 | 1: | ||
| 134 | #endif | ||
| 135 | /* | ||
| 136 | * Here by mistake? This is possible, what can happen is that by the | ||
| 137 | * time we take the exception the IRQ pin goes low, so just leave if | ||
| 138 | * this is the case. | ||
| 139 | */ | ||
| 140 | move a1,s0 | ||
| 141 | PRINT("Got interrupt: c0_cause = %08x\n") | ||
| 142 | mfc0 a1, CP0_EPC | ||
| 143 | PRINT("c0_epc = %08x\n") | ||
| 144 | |||
| 145 | j ret_from_irq | ||
| 146 | nop | ||
| 147 | END(mipsIRQ) | ||