diff options
Diffstat (limited to 'arch/mips/mips-boards/malta/malta_smtc.c')
-rw-r--r-- | arch/mips/mips-boards/malta/malta_smtc.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c index 0fb4c269901c..ae05d058cb37 100644 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ b/arch/mips/mips-boards/malta/malta_smtc.c | |||
@@ -1,6 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Malta Platform-specific hooks for SMP operation | 2 | * Malta Platform-specific hooks for SMP operation |
3 | */ | 3 | */ |
4 | #include <linux/irq.h> | ||
4 | #include <linux/init.h> | 5 | #include <linux/init.h> |
5 | 6 | ||
6 | #include <asm/mipsregs.h> | 7 | #include <asm/mipsregs.h> |
@@ -24,7 +25,7 @@ void core_send_ipi(int cpu, unsigned int action) | |||
24 | * Platform "CPU" startup hook | 25 | * Platform "CPU" startup hook |
25 | */ | 26 | */ |
26 | 27 | ||
27 | void prom_boot_secondary(int cpu, struct task_struct *idle) | 28 | void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) |
28 | { | 29 | { |
29 | smtc_boot_secondary(cpu, idle); | 30 | smtc_boot_secondary(cpu, idle); |
30 | } | 31 | } |
@@ -33,7 +34,7 @@ void prom_boot_secondary(int cpu, struct task_struct *idle) | |||
33 | * Post-config but pre-boot cleanup entry point | 34 | * Post-config but pre-boot cleanup entry point |
34 | */ | 35 | */ |
35 | 36 | ||
36 | void prom_init_secondary(void) | 37 | void __cpuinit prom_init_secondary(void) |
37 | { | 38 | { |
38 | void smtc_init_secondary(void); | 39 | void smtc_init_secondary(void); |
39 | int myvpe; | 40 | int myvpe; |
@@ -42,10 +43,11 @@ void prom_init_secondary(void) | |||
42 | myvpe = read_c0_tcbind() & TCBIND_CURVPE; | 43 | myvpe = read_c0_tcbind() & TCBIND_CURVPE; |
43 | if (myvpe != 0) { | 44 | if (myvpe != 0) { |
44 | /* Ideally, this should be done only once per VPE, but... */ | 45 | /* Ideally, this should be done only once per VPE, but... */ |
45 | clear_c0_status(STATUSF_IP2); | 46 | clear_c0_status(ST0_IM); |
46 | set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3 | 47 | set_c0_status((0x100 << cp0_compare_irq) |
47 | | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 | 48 | | (0x100 << MIPS_CPU_IPI_IRQ)); |
48 | | STATUSF_IP7); | 49 | if (cp0_perfcount_irq >= 0) |
50 | set_c0_status(0x100 << cp0_perfcount_irq); | ||
49 | } | 51 | } |
50 | 52 | ||
51 | smtc_init_secondary(); | 53 | smtc_init_secondary(); |
@@ -74,7 +76,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus) | |||
74 | * SMP initialization finalization entry point | 76 | * SMP initialization finalization entry point |
75 | */ | 77 | */ |
76 | 78 | ||
77 | void prom_smp_finish(void) | 79 | void __cpuinit prom_smp_finish(void) |
78 | { | 80 | { |
79 | smtc_smp_finish(); | 81 | smtc_smp_finish(); |
80 | } | 82 | } |