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Diffstat (limited to 'arch/mips/mips-boards/malta/malta_int.c')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 7cc0ba4f553a..ed221dc7f6ac 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -114,7 +114,7 @@ static inline int get_int(void)
114 return irq; 114 return irq;
115} 115}
116 116
117static void malta_hw0_irqdispatch(struct pt_regs *regs) 117static void malta_hw0_irqdispatch(void)
118{ 118{
119 int irq; 119 int irq;
120 120
@@ -123,17 +123,21 @@ static void malta_hw0_irqdispatch(struct pt_regs *regs)
123 return; /* interrupt has already been cleared */ 123 return; /* interrupt has already been cleared */
124 } 124 }
125 125
126 do_IRQ(MALTA_INT_BASE+irq, regs); 126 do_IRQ(MALTA_INT_BASE + irq);
127} 127}
128 128
129void corehi_irqdispatch(struct pt_regs *regs) 129static void corehi_irqdispatch(void)
130{ 130{
131 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
132 unsigned int pcimstat, intisr, inten, intpol;
131 unsigned int intrcause,datalo,datahi; 133 unsigned int intrcause,datalo,datahi;
132 unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr; 134 struct pt_regs *regs;
133 135
134 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 136 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
135 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" 137 printk("epc : %08lx\nStatus: %08lx\n"
136, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); 138 "Cause : %08lx\nbadVaddr : %08lx\n",
139 regs->cp0_epc, regs->cp0_status,
140 regs->cp0_cause, regs->cp0_badvaddr);
137 141
138 /* Read all the registers and then print them as there is a 142 /* Read all the registers and then print them as there is a
139 problem with interspersed printk's upsetting the Bonito controller. 143 problem with interspersed printk's upsetting the Bonito controller.
@@ -146,7 +150,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
146 case MIPS_REVISION_CORID_CORE_FPGA3: 150 case MIPS_REVISION_CORID_CORE_FPGA3:
147 case MIPS_REVISION_CORID_CORE_24K: 151 case MIPS_REVISION_CORID_CORE_24K:
148 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 152 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
149 ll_msc_irq(regs); 153 ll_msc_irq();
150 break; 154 break;
151 case MIPS_REVISION_CORID_QED_RM5261: 155 case MIPS_REVISION_CORID_QED_RM5261:
152 case MIPS_REVISION_CORID_CORE_LV: 156 case MIPS_REVISION_CORID_CORE_LV:
@@ -255,7 +259,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
255 * another exception, big deal. 259 * another exception, big deal.
256 */ 260 */
257 261
258asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 262asmlinkage void plat_irq_dispatch(void)
259{ 263{
260 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 264 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
261 int irq; 265 int irq;
@@ -263,11 +267,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
263 irq = irq_ffs(pending); 267 irq = irq_ffs(pending);
264 268
265 if (irq == MIPSCPU_INT_I8259A) 269 if (irq == MIPSCPU_INT_I8259A)
266 malta_hw0_irqdispatch(regs); 270 malta_hw0_irqdispatch();
267 else if (irq > 0) 271 else if (irq > 0)
268 do_IRQ(MIPSCPU_INT_BASE + irq, regs); 272 do_IRQ(MIPSCPU_INT_BASE + irq);
269 else 273 else
270 spurious_interrupt(regs); 274 spurious_interrupt();
271} 275}
272 276
273static struct irqaction i8259irq = { 277static struct irqaction i8259irq = {