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-rw-r--r--arch/mips/mips-boards/generic/Makefile29
-rw-r--r--arch/mips/mips-boards/generic/amon.c80
-rw-r--r--arch/mips/mips-boards/generic/cmdline.c59
-rw-r--r--arch/mips/mips-boards/generic/console.c68
-rw-r--r--arch/mips/mips-boards/generic/display.c63
-rw-r--r--arch/mips/mips-boards/generic/gdb_hook.c133
-rw-r--r--arch/mips/mips-boards/generic/init.c436
-rw-r--r--arch/mips/mips-boards/generic/memory.c183
-rw-r--r--arch/mips/mips-boards/generic/pci.c243
-rw-r--r--arch/mips/mips-boards/generic/reset.c75
-rw-r--r--arch/mips/mips-boards/generic/time.c186
11 files changed, 0 insertions, 1555 deletions
diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile
deleted file mode 100644
index f7f87fc09d1e..000000000000
--- a/arch/mips/mips-boards/generic/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# This program is free software; you can distribute it and/or modify it
6# under the terms of the GNU General Public License (Version 2) as
7# published by the Free Software Foundation.
8#
9# This program is distributed in the hope it will be useful, but WITHOUT
10# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12# for more details.
13#
14# You should have received a copy of the GNU General Public License along
15# with this program; if not, write to the Free Software Foundation, Inc.,
16# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17#
18# Makefile for the MIPS boards generic routines under Linux.
19#
20
21obj-y := reset.o display.o init.o memory.o \
22 cmdline.o time.o
23obj-y += amon.o
24
25obj-$(CONFIG_EARLY_PRINTK) += console.o
26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
28
29EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c
deleted file mode 100644
index 96236bf33838..000000000000
--- a/arch/mips/mips-boards/generic/amon.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Copyright (C) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Arbitrary Monitor interface
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/smp.h>
24
25#include <asm-mips/addrspace.h>
26#include <asm-mips/mips-boards/launch.h>
27#include <asm-mips/mipsmtregs.h>
28
29int amon_cpu_avail(int cpu)
30{
31 struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
32
33 if (cpu < 0 || cpu >= NCPULAUNCH) {
34 pr_debug("avail: cpu%d is out of range\n", cpu);
35 return 0;
36 }
37
38 launch += cpu;
39 if (!(launch->flags & LAUNCH_FREADY)) {
40 pr_debug("avail: cpu%d is not ready\n", cpu);
41 return 0;
42 }
43 if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
44 pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
45 return 0;
46 }
47
48 return 1;
49}
50
51void amon_cpu_start(int cpu,
52 unsigned long pc, unsigned long sp,
53 unsigned long gp, unsigned long a0)
54{
55 volatile struct cpulaunch *launch =
56 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
57
58 if (!amon_cpu_avail(cpu))
59 return;
60 if (cpu == smp_processor_id()) {
61 pr_debug("launch: I am cpu%d!\n", cpu);
62 return;
63 }
64 launch += cpu;
65
66 pr_debug("launch: starting cpu%d\n", cpu);
67
68 launch->pc = pc;
69 launch->gp = gp;
70 launch->sp = sp;
71 launch->a0 = a0;
72
73 /* Make sure target sees parameters before the go bit */
74 smp_mb();
75
76 launch->flags |= LAUNCH_FGO;
77 while ((launch->flags & LAUNCH_FGONE) == 0)
78 ;
79 pr_debug("launch: cpu%d gone!\n", cpu);
80}
diff --git a/arch/mips/mips-boards/generic/cmdline.c b/arch/mips/mips-boards/generic/cmdline.c
deleted file mode 100644
index 1871c30ed2eb..000000000000
--- a/arch/mips/mips-boards/generic/cmdline.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Kernel command line creation using the prom monitor (YAMON) argc/argv.
19 */
20#include <linux/init.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24
25extern int prom_argc;
26extern int *_prom_argv;
27
28/*
29 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
30 * This macro take care of sign extension.
31 */
32#define prom_argv(index) ((char *)(long)_prom_argv[(index)])
33
34char * __init prom_getcmdline(void)
35{
36 return &(arcs_cmdline[0]);
37}
38
39
40void __init prom_init_cmdline(void)
41{
42 char *cp;
43 int actr;
44
45 actr = 1; /* Always ignore argv[0] */
46
47 cp = &(arcs_cmdline[0]);
48 while(actr < prom_argc) {
49 strcpy(cp, prom_argv(actr));
50 cp += strlen(prom_argv(actr));
51 *cp++ = ' ';
52 actr++;
53 }
54 if (cp != &(arcs_cmdline[0])) {
55 /* get rid of trailing space */
56 --cp;
57 *cp = '\0';
58 }
59}
diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c
deleted file mode 100644
index 4d8ab99e4155..000000000000
--- a/arch/mips/mips-boards/generic/console.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Putting things on the screen/serial line using YAMONs facilities.
19 */
20#include <linux/console.h>
21#include <linux/init.h>
22#include <linux/serial_reg.h>
23#include <asm/io.h>
24
25#ifdef CONFIG_MIPS_ATLAS
26#include <asm/mips-boards/atlas.h>
27
28#ifdef CONFIG_CPU_LITTLE_ENDIAN
29#define PORT(offset) (ATLAS_UART_REGS_BASE + ((offset)<<3))
30#else
31#define PORT(offset) (ATLAS_UART_REGS_BASE + 3 + ((offset)<<3))
32#endif
33
34#elif defined(CONFIG_MIPS_SEAD)
35
36#include <asm/mips-boards/sead.h>
37
38#ifdef CONFIG_CPU_LITTLE_ENDIAN
39#define PORT(offset) (SEAD_UART0_REGS_BASE + ((offset)<<3))
40#else
41#define PORT(offset) (SEAD_UART0_REGS_BASE + 3 + ((offset)<<3))
42#endif
43
44#else
45
46#define PORT(offset) (0x3f8 + (offset))
47
48#endif
49
50static inline unsigned int serial_in(int offset)
51{
52 return inb(PORT(offset));
53}
54
55static inline void serial_out(int offset, int value)
56{
57 outb(value, PORT(offset));
58}
59
60int prom_putchar(char c)
61{
62 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
63 ;
64
65 serial_out(UART_TX, c);
66
67 return 1;
68}
diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c
deleted file mode 100644
index 2a0057cfc30d..000000000000
--- a/arch/mips/mips-boards/generic/display.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Display routines for display messages in MIPS boards ascii display.
19 */
20
21#include <linux/compiler.h>
22#include <linux/timer.h>
23#include <asm/io.h>
24#include <asm/mips-boards/generic.h>
25
26extern const char display_string[];
27static unsigned int display_count;
28static unsigned int max_display_count;
29
30void mips_display_message(const char *str)
31{
32 static unsigned int __iomem *display = NULL;
33 int i;
34
35 if (unlikely(display == NULL))
36 display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int));
37
38 for (i = 0; i <= 14; i=i+2) {
39 if (*str)
40 __raw_writel(*str++, display + i);
41 else
42 __raw_writel(' ', display + i);
43 }
44}
45
46static void scroll_display_message(unsigned long data);
47static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0);
48
49static void scroll_display_message(unsigned long data)
50{
51 mips_display_message(&display_string[display_count++]);
52 if (display_count == max_display_count)
53 display_count = 0;
54
55 mod_timer(&mips_scroll_timer, jiffies + HZ);
56}
57
58void mips_scroll_message(void)
59{
60 del_timer_sync(&mips_scroll_timer);
61 max_display_count = strlen(display_string) + 1 - 8;
62 mod_timer(&mips_scroll_timer, jiffies + 1);
63}
diff --git a/arch/mips/mips-boards/generic/gdb_hook.c b/arch/mips/mips-boards/generic/gdb_hook.c
deleted file mode 100644
index 6a1854de4579..000000000000
--- a/arch/mips/mips-boards/generic/gdb_hook.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * This is the interface to the remote debugger stub.
19 */
20#include <linux/types.h>
21#include <linux/serial.h>
22#include <linux/serialP.h>
23#include <linux/serial_reg.h>
24
25#include <asm/serial.h>
26#include <asm/io.h>
27
28static struct serial_state rs_table[] = {
29 SERIAL_PORT_DFNS /* Defined in serial.h */
30};
31
32static struct async_struct kdb_port_info = {0};
33
34int (*generic_putDebugChar)(char);
35char (*generic_getDebugChar)(void);
36
37static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
38{
39 return inb(info->port + offset);
40}
41
42static __inline__ void serial_out(struct async_struct *info, int offset,
43 int value)
44{
45 outb(value, info->port+offset);
46}
47
48int rs_kgdb_hook(int tty_no, int speed) {
49 int t;
50 struct serial_state *ser = &rs_table[tty_no];
51
52 kdb_port_info.state = ser;
53 kdb_port_info.magic = SERIAL_MAGIC;
54 kdb_port_info.port = ser->port;
55 kdb_port_info.flags = ser->flags;
56
57 /*
58 * Clear all interrupts
59 */
60 serial_in(&kdb_port_info, UART_LSR);
61 serial_in(&kdb_port_info, UART_RX);
62 serial_in(&kdb_port_info, UART_IIR);
63 serial_in(&kdb_port_info, UART_MSR);
64
65 /*
66 * Now, initialize the UART
67 */
68 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
69 if (kdb_port_info.flags & ASYNC_FOURPORT) {
70 kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
71 t = UART_MCR_DTR | UART_MCR_OUT1;
72 } else {
73 kdb_port_info.MCR
74 = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
75 t = UART_MCR_DTR | UART_MCR_RTS;
76 }
77
78 kdb_port_info.MCR = t; /* no interrupts, please */
79 serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
80
81 /*
82 * and set the speed of the serial port
83 */
84 if (speed == 0)
85 speed = 9600;
86
87 t = kdb_port_info.state->baud_base / speed;
88 /* set DLAB */
89 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
90 serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
91 serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */
92 /* reset DLAB */
93 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
94
95 return speed;
96}
97
98int putDebugChar(char c)
99{
100 return generic_putDebugChar(c);
101}
102
103char getDebugChar(void)
104{
105 return generic_getDebugChar();
106}
107
108int rs_putDebugChar(char c)
109{
110
111 if (!kdb_port_info.state) { /* need to init device first */
112 return 0;
113 }
114
115 while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
116 ;
117
118 serial_out(&kdb_port_info, UART_TX, c);
119
120 return 1;
121}
122
123char rs_getDebugChar(void)
124{
125 if (!kdb_port_info.state) { /* need to init device first */
126 return 0;
127 }
128
129 while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
130 ;
131
132 return serial_in(&kdb_port_info, UART_RX);
133}
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
deleted file mode 100644
index 83b9dc739203..000000000000
--- a/arch/mips/mips-boards/generic/init.c
+++ /dev/null
@@ -1,436 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * PROM library initialisation code.
21 */
22#include <linux/init.h>
23#include <linux/string.h>
24#include <linux/kernel.h>
25
26#include <asm/bootinfo.h>
27#include <asm/gt64120.h>
28#include <asm/io.h>
29#include <asm/system.h>
30#include <asm/cacheflush.h>
31#include <asm/traps.h>
32
33#include <asm/mips-boards/prom.h>
34#include <asm/mips-boards/generic.h>
35#include <asm/mips-boards/bonito64.h>
36#include <asm/mips-boards/msc01_pci.h>
37
38#include <asm/mips-boards/malta.h>
39
40#ifdef CONFIG_KGDB
41extern int rs_kgdb_hook(int, int);
42extern int rs_putDebugChar(char);
43extern char rs_getDebugChar(void);
44extern int saa9730_kgdb_hook(int);
45extern int saa9730_putDebugChar(char);
46extern char saa9730_getDebugChar(void);
47#endif
48
49int prom_argc;
50int *_prom_argv, *_prom_envp;
51
52/*
53 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
54 * This macro take care of sign extension, if running in 64-bit mode.
55 */
56#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
57
58int init_debug = 0;
59
60int mips_revision_corid;
61int mips_revision_sconid;
62
63/* Bonito64 system controller register base. */
64unsigned long _pcictrl_bonito;
65unsigned long _pcictrl_bonito_pcicfg;
66
67/* GT64120 system controller register base */
68unsigned long _pcictrl_gt64120;
69
70/* MIPS System controller register base */
71unsigned long _pcictrl_msc;
72
73char *prom_getenv(char *envname)
74{
75 /*
76 * Return a pointer to the given environment variable.
77 * In 64-bit mode: we're using 64-bit pointers, but all pointers
78 * in the PROM structures are only 32-bit, so we need some
79 * workarounds, if we are running in 64-bit mode.
80 */
81 int i, index=0;
82
83 i = strlen(envname);
84
85 while (prom_envp(index)) {
86 if(strncmp(envname, prom_envp(index), i) == 0) {
87 return(prom_envp(index+1));
88 }
89 index += 2;
90 }
91
92 return NULL;
93}
94
95static inline unsigned char str2hexnum(unsigned char c)
96{
97 if (c >= '0' && c <= '9')
98 return c - '0';
99 if (c >= 'a' && c <= 'f')
100 return c - 'a' + 10;
101 return 0; /* foo */
102}
103
104static inline void str2eaddr(unsigned char *ea, unsigned char *str)
105{
106 int i;
107
108 for (i = 0; i < 6; i++) {
109 unsigned char num;
110
111 if((*str == '.') || (*str == ':'))
112 str++;
113 num = str2hexnum(*str++) << 4;
114 num |= (str2hexnum(*str++));
115 ea[i] = num;
116 }
117}
118
119int get_ethernet_addr(char *ethernet_addr)
120{
121 char *ethaddr_str;
122
123 ethaddr_str = prom_getenv("ethaddr");
124 if (!ethaddr_str) {
125 printk("ethaddr not set in boot prom\n");
126 return -1;
127 }
128 str2eaddr(ethernet_addr, ethaddr_str);
129
130 if (init_debug > 1) {
131 int i;
132 printk("get_ethernet_addr: ");
133 for (i=0; i<5; i++)
134 printk("%02x:", (unsigned char)*(ethernet_addr+i));
135 printk("%02x\n", *(ethernet_addr+i));
136 }
137
138 return 0;
139}
140
141#ifdef CONFIG_SERIAL_8250_CONSOLE
142static void __init console_config(void)
143{
144 char console_string[40];
145 int baud = 0;
146 char parity = '\0', bits = '\0', flow = '\0';
147 char *s;
148
149 if ((strstr(prom_getcmdline(), "console=")) == NULL) {
150 s = prom_getenv("modetty0");
151 if (s) {
152 while (*s >= '0' && *s <= '9')
153 baud = baud*10 + *s++ - '0';
154 if (*s == ',') s++;
155 if (*s) parity = *s++;
156 if (*s == ',') s++;
157 if (*s) bits = *s++;
158 if (*s == ',') s++;
159 if (*s == 'h') flow = 'r';
160 }
161 if (baud == 0)
162 baud = 38400;
163 if (parity != 'n' && parity != 'o' && parity != 'e')
164 parity = 'n';
165 if (bits != '7' && bits != '8')
166 bits = '8';
167 if (flow == '\0')
168 flow = 'r';
169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
170 strcat(prom_getcmdline(), console_string);
171 pr_info("Config serial console:%s\n", console_string);
172 }
173}
174#endif
175
176#ifdef CONFIG_KGDB
177void __init kgdb_config(void)
178{
179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void);
181 char *argptr;
182 int line, speed;
183
184 argptr = prom_getcmdline();
185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
186 argptr += strlen("kgdb=ttyS");
187 if (*argptr != '0' && *argptr != '1')
188 printk("KGDB: Unknown serial line /dev/ttyS%c, "
189 "falling back to /dev/ttyS1\n", *argptr);
190 line = *argptr == '0' ? 0 : 1;
191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
192
193 speed = 0;
194 if (*++argptr == ',')
195 {
196 int c;
197 while ((c = *++argptr) && ('0' <= c && c <= '9'))
198 speed = speed * 10 + c - '0';
199 }
200#ifdef CONFIG_MIPS_ATLAS
201 if (line == 1) {
202 speed = saa9730_kgdb_hook(speed);
203 generic_putDebugChar = saa9730_putDebugChar;
204 generic_getDebugChar = saa9730_getDebugChar;
205 }
206 else
207#endif
208 {
209 speed = rs_kgdb_hook(line, speed);
210 generic_putDebugChar = rs_putDebugChar;
211 generic_getDebugChar = rs_getDebugChar;
212 }
213
214 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
215 "session, please connect your debugger\n",
216 line ? 1 : 0, speed);
217
218 {
219 char *s;
220 for (s = "Please connect GDB to this port\r\n"; *s; )
221 generic_putDebugChar(*s++);
222 }
223
224 /* Breakpoint is invoked after interrupts are initialised */
225 }
226}
227#endif
228
229static void __init mips_nmi_setup(void)
230{
231 void *base;
232 extern char except_vec_nmi;
233
234 base = cpu_has_veic ?
235 (void *)(CAC_BASE + 0xa80) :
236 (void *)(CAC_BASE + 0x380);
237 memcpy(base, &except_vec_nmi, 0x80);
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
239}
240
241static void __init mips_ejtag_setup(void)
242{
243 void *base;
244 extern char except_vec_ejtag_debug;
245
246 base = cpu_has_veic ?
247 (void *)(CAC_BASE + 0xa00) :
248 (void *)(CAC_BASE + 0x300);
249 memcpy(base, &except_vec_ejtag_debug, 0x80);
250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
251}
252
253extern struct plat_smp_ops msmtc_smp_ops;
254
255void __init prom_init(void)
256{
257 prom_argc = fw_arg0;
258 _prom_argv = (int *) fw_arg1;
259 _prom_envp = (int *) fw_arg2;
260
261 mips_display_message("LINUX");
262
263#ifdef CONFIG_MIPS_SEAD
264 set_io_port_base(KSEG1);
265#else
266 /*
267 * early setup of _pcictrl_bonito so that we can determine
268 * the system controller on a CORE_EMUL board
269 */
270 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
271
272 mips_revision_corid = MIPS_REVISION_CORID;
273
274 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
275 if (BONITO_PCIDID == 0x0001df53 ||
276 BONITO_PCIDID == 0x0003df53)
277 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
278 else
279 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
280 }
281
282 mips_revision_sconid = MIPS_REVISION_SCONID;
283 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
284 switch (mips_revision_corid) {
285 case MIPS_REVISION_CORID_QED_RM5261:
286 case MIPS_REVISION_CORID_CORE_LV:
287 case MIPS_REVISION_CORID_CORE_FPGA:
288 case MIPS_REVISION_CORID_CORE_FPGAR2:
289 mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
290 break;
291 case MIPS_REVISION_CORID_CORE_EMUL_BON:
292 case MIPS_REVISION_CORID_BONITO64:
293 case MIPS_REVISION_CORID_CORE_20K:
294 mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
295 break;
296 case MIPS_REVISION_CORID_CORE_MSC:
297 case MIPS_REVISION_CORID_CORE_FPGA2:
298 case MIPS_REVISION_CORID_CORE_24K:
299 /*
300 * SOCit/ROCit support is essentially identical
301 * but make an attempt to distinguish them
302 */
303 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
304 break;
305 case MIPS_REVISION_CORID_CORE_FPGA3:
306 case MIPS_REVISION_CORID_CORE_FPGA4:
307 case MIPS_REVISION_CORID_CORE_FPGA5:
308 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
309 default:
310 /* See above */
311 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
312 break;
313 }
314 }
315
316 switch (mips_revision_sconid) {
317 u32 start, map, mask, data;
318
319 case MIPS_REVISION_SCON_GT64120:
320 /*
321 * Setup the North bridge to do Master byte-lane swapping
322 * when running in bigendian.
323 */
324 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
325
326#ifdef CONFIG_CPU_LITTLE_ENDIAN
327 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
328 GT_PCI0_CMD_SBYTESWAP_BIT);
329#else
330 GT_WRITE(GT_PCI0_CMD_OFS, 0);
331#endif
332 /* Fix up PCI I/O mapping if necessary (for Atlas). */
333 start = GT_READ(GT_PCI0IOLD_OFS);
334 map = GT_READ(GT_PCI0IOREMAP_OFS);
335 if ((start & map) != 0) {
336 map &= ~start;
337 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
338 }
339
340 set_io_port_base(MALTA_GT_PORT_BASE);
341 break;
342
343 case MIPS_REVISION_SCON_BONITO:
344 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
345
346 /*
347 * Disable Bonito IOBC.
348 */
349 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
350 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
351 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
352
353 /*
354 * Setup the North bridge to do Master byte-lane swapping
355 * when running in bigendian.
356 */
357#ifdef CONFIG_CPU_LITTLE_ENDIAN
358 BONITO_BONGENCFG = BONITO_BONGENCFG &
359 ~(BONITO_BONGENCFG_MSTRBYTESWAP |
360 BONITO_BONGENCFG_BYTESWAP);
361#else
362 BONITO_BONGENCFG = BONITO_BONGENCFG |
363 BONITO_BONGENCFG_MSTRBYTESWAP |
364 BONITO_BONGENCFG_BYTESWAP;
365#endif
366
367 set_io_port_base(MALTA_BONITO_PORT_BASE);
368 break;
369
370 case MIPS_REVISION_SCON_SOCIT:
371 case MIPS_REVISION_SCON_ROCIT:
372 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
373 mips_pci_controller:
374 mb();
375 MSC_READ(MSC01_PCI_CFG, data);
376 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
377 wmb();
378
379 /* Fix up lane swapping. */
380#ifdef CONFIG_CPU_LITTLE_ENDIAN
381 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
382#else
383 MSC_WRITE(MSC01_PCI_SWAP,
384 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
385 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
386 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
387#endif
388 /* Fix up target memory mapping. */
389 MSC_READ(MSC01_PCI_BAR0, mask);
390 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
391
392 /* Don't handle target retries indefinitely. */
393 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
394 MSC01_PCI_CFG_MAXRTRY_MSK)
395 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
396 MSC01_PCI_CFG_MAXRTRY_SHF)) |
397 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
398 MSC01_PCI_CFG_MAXRTRY_SHF);
399
400 wmb();
401 MSC_WRITE(MSC01_PCI_CFG, data);
402 mb();
403
404 set_io_port_base(MALTA_MSC_PORT_BASE);
405 break;
406
407 case MIPS_REVISION_SCON_SOCITSC:
408 case MIPS_REVISION_SCON_SOCITSCP:
409 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
410 goto mips_pci_controller;
411
412 default:
413 /* Unknown system controller */
414 mips_display_message("SC Error");
415 while (1); /* We die here... */
416 }
417#endif
418 board_nmi_handler_setup = mips_nmi_setup;
419 board_ejtag_handler_setup = mips_ejtag_setup;
420
421 pr_info("\nLINUX started...\n");
422 prom_init_cmdline();
423 prom_meminit();
424#ifdef CONFIG_SERIAL_8250_CONSOLE
425 console_config();
426#endif
427#ifdef CONFIG_MIPS_CMP
428 register_smp_ops(&cmp_smp_ops);
429#endif
430#ifdef CONFIG_MIPS_MT_SMP
431 register_smp_ops(&vsmp_smp_ops);
432#endif
433#ifdef CONFIG_MIPS_MT_SMTC
434 register_smp_ops(&msmtc_smp_ops);
435#endif
436}
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
deleted file mode 100644
index 5e443bba5662..000000000000
--- a/arch/mips/mips-boards/generic/memory.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * PROM library functions for acquiring/using memory descriptors given to
19 * us from the YAMON.
20 */
21#include <linux/init.h>
22#include <linux/mm.h>
23#include <linux/bootmem.h>
24#include <linux/pfn.h>
25#include <linux/string.h>
26
27#include <asm/bootinfo.h>
28#include <asm/page.h>
29#include <asm/sections.h>
30
31#include <asm/mips-boards/prom.h>
32
33/*#define DEBUG*/
34
35enum yamon_memtypes {
36 yamon_dontuse,
37 yamon_prom,
38 yamon_free,
39};
40static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
41
42#ifdef DEBUG
43static char *mtypes[3] = {
44 "Dont use memory",
45 "YAMON PROM memory",
46 "Free memmory",
47};
48#endif
49
50/* determined physical memory size, not overridden by command line args */
51unsigned long physical_memsize = 0L;
52
53static struct prom_pmemblock * __init prom_getmdesc(void)
54{
55 char *memsize_str;
56 unsigned int memsize;
57 char cmdline[CL_SIZE], *ptr;
58
59 /* otherwise look in the environment */
60 memsize_str = prom_getenv("memsize");
61 if (!memsize_str) {
62 printk(KERN_WARNING
63 "memsize not set in boot prom, set to default (32Mb)\n");
64 physical_memsize = 0x02000000;
65 } else {
66#ifdef DEBUG
67 pr_debug("prom_memsize = %s\n", memsize_str);
68#endif
69 physical_memsize = simple_strtol(memsize_str, NULL, 0);
70 }
71
72#ifdef CONFIG_CPU_BIG_ENDIAN
73 /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
74 word of physical memory */
75 physical_memsize -= PAGE_SIZE;
76#endif
77
78 /* Check the command line for a memsize directive that overrides
79 the physical/default amount */
80 strcpy(cmdline, arcs_cmdline);
81 ptr = strstr(cmdline, "memsize=");
82 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
83 ptr = strstr(ptr, " memsize=");
84
85 if (ptr)
86 memsize = memparse(ptr + 8, &ptr);
87 else
88 memsize = physical_memsize;
89
90 memset(mdesc, 0, sizeof(mdesc));
91
92 mdesc[0].type = yamon_dontuse;
93 mdesc[0].base = 0x00000000;
94 mdesc[0].size = 0x00001000;
95
96 mdesc[1].type = yamon_prom;
97 mdesc[1].base = 0x00001000;
98 mdesc[1].size = 0x000ef000;
99
100#ifdef CONFIG_MIPS_MALTA
101 /*
102 * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
103 * south bridge and PCI access always forwarded to the ISA Bus and
104 * BIOSCS# is always generated.
105 * This mean that this area can't be used as DMA memory for PCI
106 * devices.
107 */
108 mdesc[2].type = yamon_dontuse;
109 mdesc[2].base = 0x000f0000;
110 mdesc[2].size = 0x00010000;
111#else
112 mdesc[2].type = yamon_prom;
113 mdesc[2].base = 0x000f0000;
114 mdesc[2].size = 0x00010000;
115#endif
116
117 mdesc[3].type = yamon_dontuse;
118 mdesc[3].base = 0x00100000;
119 mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base;
120
121 mdesc[4].type = yamon_free;
122 mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
123 mdesc[4].size = memsize - mdesc[4].base;
124
125 return &mdesc[0];
126}
127
128static int __init prom_memtype_classify(unsigned int type)
129{
130 switch (type) {
131 case yamon_free:
132 return BOOT_MEM_RAM;
133 case yamon_prom:
134 return BOOT_MEM_ROM_DATA;
135 default:
136 return BOOT_MEM_RESERVED;
137 }
138}
139
140void __init prom_meminit(void)
141{
142 struct prom_pmemblock *p;
143
144#ifdef DEBUG
145 pr_debug("YAMON MEMORY DESCRIPTOR dump:\n");
146 p = prom_getmdesc();
147 while (p->size) {
148 int i = 0;
149 pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n",
150 i, p, p->base, p->size, mtypes[p->type]);
151 p++;
152 i++;
153 }
154#endif
155 p = prom_getmdesc();
156
157 while (p->size) {
158 long type;
159 unsigned long base, size;
160
161 type = prom_memtype_classify(p->type);
162 base = p->base;
163 size = p->size;
164
165 add_memory_region(base, size, type);
166 p++;
167 }
168}
169
170void __init prom_free_prom_memory(void)
171{
172 unsigned long addr;
173 int i;
174
175 for (i = 0; i < boot_mem_map.nr_map; i++) {
176 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
177 continue;
178
179 addr = boot_mem_map.map[i].addr;
180 free_init_pages("prom memory",
181 addr, addr + boot_mem_map.map[i].size);
182 }
183}
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
deleted file mode 100644
index b9743190609a..000000000000
--- a/arch/mips/mips-boards/generic/pci.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 *
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * MIPS boards specific PCI support.
23 */
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/kernel.h>
27#include <linux/init.h>
28
29#include <asm/gt64120.h>
30
31#include <asm/mips-boards/generic.h>
32#include <asm/mips-boards/bonito64.h>
33#include <asm/mips-boards/msc01_pci.h>
34
35static struct resource bonito64_mem_resource = {
36 .name = "Bonito PCI MEM",
37 .flags = IORESOURCE_MEM,
38};
39
40static struct resource bonito64_io_resource = {
41 .name = "Bonito PCI I/O",
42 .start = 0x00000000UL,
43 .end = 0x000fffffUL,
44 .flags = IORESOURCE_IO,
45};
46
47static struct resource gt64120_mem_resource = {
48 .name = "GT-64120 PCI MEM",
49 .flags = IORESOURCE_MEM,
50};
51
52static struct resource gt64120_io_resource = {
53 .name = "GT-64120 PCI I/O",
54 .flags = IORESOURCE_IO,
55};
56
57static struct resource msc_mem_resource = {
58 .name = "MSC PCI MEM",
59 .flags = IORESOURCE_MEM,
60};
61
62static struct resource msc_io_resource = {
63 .name = "MSC PCI I/O",
64 .flags = IORESOURCE_IO,
65};
66
67extern struct pci_ops bonito64_pci_ops;
68extern struct pci_ops gt64xxx_pci0_ops;
69extern struct pci_ops msc_pci_ops;
70
71static struct pci_controller bonito64_controller = {
72 .pci_ops = &bonito64_pci_ops,
73 .io_resource = &bonito64_io_resource,
74 .mem_resource = &bonito64_mem_resource,
75 .io_offset = 0x00000000UL,
76};
77
78static struct pci_controller gt64120_controller = {
79 .pci_ops = &gt64xxx_pci0_ops,
80 .io_resource = &gt64120_io_resource,
81 .mem_resource = &gt64120_mem_resource,
82};
83
84static struct pci_controller msc_controller = {
85 .pci_ops = &msc_pci_ops,
86 .io_resource = &msc_io_resource,
87 .mem_resource = &msc_mem_resource,
88};
89
90void __init mips_pcibios_init(void)
91{
92 struct pci_controller *controller;
93 resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
94
95 switch (mips_revision_sconid) {
96 case MIPS_REVISION_SCON_GT64120:
97 /*
98 * Due to a bug in the Galileo system controller, we need
99 * to setup the PCI BAR for the Galileo internal registers.
100 * This should be done in the bios/bootprom and will be
101 * fixed in a later revision of YAMON (the MIPS boards
102 * boot prom).
103 */
104 GT_WRITE(GT_PCI0_CFGADDR_OFS,
105 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
106 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
107 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
108 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
109 GT_PCI0_CFGADDR_CONFIGEN_BIT);
110
111 /* Perform the write */
112 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
113
114 /* Set up resource ranges from the controller's registers. */
115 start = GT_READ(GT_PCI0M0LD_OFS);
116 end = GT_READ(GT_PCI0M0HD_OFS);
117 map = GT_READ(GT_PCI0M0REMAP_OFS);
118 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
119 start1 = GT_READ(GT_PCI0M1LD_OFS);
120 end1 = GT_READ(GT_PCI0M1HD_OFS);
121 map1 = GT_READ(GT_PCI0M1REMAP_OFS);
122 end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
123 /* Cannot support multiple windows, use the wider. */
124 if (end1 - start1 > end - start) {
125 start = start1;
126 end = end1;
127 map = map1;
128 }
129 mask = ~(start ^ end);
130 /* We don't support remapping with a discontiguous mask. */
131 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
132 mask != ~((mask & -mask) - 1));
133 gt64120_mem_resource.start = start;
134 gt64120_mem_resource.end = end;
135 gt64120_controller.mem_offset = (start & mask) - (map & mask);
136 /* Addresses are 36-bit, so do shifts in the destinations. */
137 gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
138 gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
139 gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
140 gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
141
142 start = GT_READ(GT_PCI0IOLD_OFS);
143 end = GT_READ(GT_PCI0IOHD_OFS);
144 map = GT_READ(GT_PCI0IOREMAP_OFS);
145 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
146 mask = ~(start ^ end);
147 /* We don't support remapping with a discontiguous mask. */
148 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
149 mask != ~((mask & -mask) - 1));
150 gt64120_io_resource.start = map & mask;
151 gt64120_io_resource.end = (map & mask) | ~mask;
152 gt64120_controller.io_offset = 0;
153 /* Addresses are 36-bit, so do shifts in the destinations. */
154 gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
155 gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
156 gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
157
158 controller = &gt64120_controller;
159 break;
160
161 case MIPS_REVISION_SCON_BONITO:
162 /* Set up resource ranges from the controller's registers. */
163 map = BONITO_PCIMAP;
164 map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
165 BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
166 map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
167 BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
168 map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
169 BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
170 /* Combine as many adjacent windows as possible. */
171 map = map1;
172 start = BONITO_PCILO0_BASE;
173 end = 1;
174 if (map3 == map2 + 1) {
175 map = map2;
176 start = BONITO_PCILO1_BASE;
177 end++;
178 }
179 if (map2 == map1 + 1) {
180 map = map1;
181 start = BONITO_PCILO0_BASE;
182 end++;
183 }
184 bonito64_mem_resource.start = start;
185 bonito64_mem_resource.end = start +
186 BONITO_PCIMAP_WINBASE(end) - 1;
187 bonito64_controller.mem_offset = start -
188 BONITO_PCIMAP_WINBASE(map);
189
190 controller = &bonito64_controller;
191 break;
192
193 case MIPS_REVISION_SCON_SOCIT:
194 case MIPS_REVISION_SCON_ROCIT:
195 case MIPS_REVISION_SCON_SOCITSC:
196 case MIPS_REVISION_SCON_SOCITSCP:
197 /* Set up resource ranges from the controller's registers. */
198 MSC_READ(MSC01_PCI_SC2PMBASL, start);
199 MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
200 MSC_READ(MSC01_PCI_SC2PMMAPL, map);
201 msc_mem_resource.start = start & mask;
202 msc_mem_resource.end = (start & mask) | ~mask;
203 msc_controller.mem_offset = (start & mask) - (map & mask);
204
205 MSC_READ(MSC01_PCI_SC2PIOBASL, start);
206 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
207 MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
208 msc_io_resource.start = map & mask;
209 msc_io_resource.end = (map & mask) | ~mask;
210 msc_controller.io_offset = 0;
211 ioport_resource.end = ~mask;
212
213 /* If ranges overlap I/O takes precedence. */
214 start = start & mask;
215 end = start | ~mask;
216 if ((start >= msc_mem_resource.start &&
217 start <= msc_mem_resource.end) ||
218 (end >= msc_mem_resource.start &&
219 end <= msc_mem_resource.end)) {
220 /* Use the larger space. */
221 start = max(start, msc_mem_resource.start);
222 end = min(end, msc_mem_resource.end);
223 if (start - msc_mem_resource.start >=
224 msc_mem_resource.end - end)
225 msc_mem_resource.end = start - 1;
226 else
227 msc_mem_resource.start = end + 1;
228 }
229
230 controller = &msc_controller;
231 break;
232 default:
233 return;
234 }
235
236 if (controller->io_resource->start < 0x00001000UL) /* FIXME */
237 controller->io_resource->start = 0x00001000UL;
238
239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
240 ioport_resource.end = controller->io_resource->end;
241
242 register_pci_controller(controller);
243}
diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c
deleted file mode 100644
index 583d468d98a9..000000000000
--- a/arch/mips/mips-boards/generic/reset.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Reset the MIPS boards.
23 *
24 */
25#include <linux/pm.h>
26
27#include <asm/io.h>
28#include <asm/reboot.h>
29#include <asm/mips-boards/generic.h>
30#if defined(CONFIG_MIPS_ATLAS)
31#include <asm/mips-boards/atlas.h>
32#endif
33
34static void mips_machine_restart(char *command);
35static void mips_machine_halt(void);
36#if defined(CONFIG_MIPS_ATLAS)
37static void atlas_machine_power_off(void);
38#endif
39
40static void mips_machine_restart(char *command)
41{
42 unsigned int __iomem *softres_reg =
43 ioremap(SOFTRES_REG, sizeof(unsigned int));
44
45 __raw_writel(GORESET, softres_reg);
46}
47
48static void mips_machine_halt(void)
49{
50 unsigned int __iomem *softres_reg =
51 ioremap(SOFTRES_REG, sizeof(unsigned int));
52
53 __raw_writel(GORESET, softres_reg);
54}
55
56#if defined(CONFIG_MIPS_ATLAS)
57static void atlas_machine_power_off(void)
58{
59 unsigned int __iomem *psustby_reg = ioremap(ATLAS_PSUSTBY_REG, sizeof(unsigned int));
60
61 writew(ATLAS_GOSTBY, psustby_reg);
62}
63#endif
64
65void mips_reboot_setup(void)
66{
67 _machine_restart = mips_machine_restart;
68 _machine_halt = mips_machine_halt;
69#if defined(CONFIG_MIPS_ATLAS)
70 pm_power_off = atlas_machine_power_off;
71#endif
72#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD)
73 pm_power_off = mips_machine_halt;
74#endif
75}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
deleted file mode 100644
index fe2cac1b4514..000000000000
--- a/arch/mips/mips-boards/generic/time.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/interrupt.h>
27#include <linux/time.h>
28#include <linux/timex.h>
29#include <linux/mc146818rtc.h>
30
31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
33#include <asm/hardirq.h>
34#include <asm/i8253.h>
35#include <asm/irq.h>
36#include <asm/div64.h>
37#include <asm/cpu.h>
38#include <asm/time.h>
39#include <asm/mc146818-time.h>
40#include <asm/msc01_ic.h>
41
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/prom.h>
44
45#ifdef CONFIG_MIPS_ATLAS
46#include <asm/mips-boards/atlasint.h>
47#endif
48#ifdef CONFIG_MIPS_MALTA
49#include <asm/mips-boards/maltaint.h>
50#endif
51#ifdef CONFIG_MIPS_SEAD
52#include <asm/mips-boards/seadint.h>
53#endif
54
55unsigned long cpu_khz;
56
57static int mips_cpu_timer_irq;
58static int mips_cpu_perf_irq;
59extern int cp0_perfcount_irq;
60
61static void mips_timer_dispatch(void)
62{
63 do_IRQ(mips_cpu_timer_irq);
64}
65
66static void mips_perf_dispatch(void)
67{
68 do_IRQ(mips_cpu_perf_irq);
69}
70
71/*
72 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
73 */
74static unsigned int __init estimate_cpu_frequency(void)
75{
76 unsigned int prid = read_c0_prid() & 0xffff00;
77 unsigned int count;
78
79#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
80 /*
81 * The SEAD board doesn't have a real time clock, so we can't
82 * really calculate the timer frequency
83 * For now we hardwire the SEAD board frequency to 12MHz.
84 */
85
86 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
87 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
88 count = 12000000;
89 else
90 count = 6000000;
91#endif
92#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
93 unsigned long flags;
94 unsigned int start;
95
96 local_irq_save(flags);
97
98 /* Start counter exactly on falling edge of update flag */
99 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
100 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
101
102 /* Start r4k counter. */
103 start = read_c0_count();
104
105 /* Read counter exactly on falling edge of update flag */
106 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
107 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
108
109 count = read_c0_count() - start;
110
111 /* restore interrupts */
112 local_irq_restore(flags);
113#endif
114
115 mips_hpt_frequency = count;
116 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
117 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
118 count *= 2;
119
120 count += 5000; /* round */
121 count -= count%10000;
122
123 return count;
124}
125
126unsigned long read_persistent_clock(void)
127{
128 return mc146818_get_cmos_time();
129}
130
131static void __init plat_perf_setup(void)
132{
133#ifdef MSC01E_INT_BASE
134 if (cpu_has_veic) {
135 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
136 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
137 } else
138#endif
139 if (cp0_perfcount_irq >= 0) {
140 if (cpu_has_vint)
141 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
142 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
143#ifdef CONFIG_SMP
144 set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
145#endif
146 }
147}
148
149unsigned int __cpuinit get_c0_compare_int(void)
150{
151#ifdef MSC01E_INT_BASE
152 if (cpu_has_veic) {
153 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
154 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
155 } else
156#endif
157 {
158 if (cpu_has_vint)
159 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
160 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
161 }
162
163 return mips_cpu_timer_irq;
164}
165
166void __init plat_time_init(void)
167{
168 unsigned int est_freq;
169
170 /* Set Data mode - binary. */
171 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
172
173 est_freq = estimate_cpu_frequency();
174
175 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
176 (est_freq%1000000)*100/1000000);
177
178 cpu_khz = est_freq / 1000;
179
180 mips_scroll_message();
181#ifdef CONFIG_I8253 /* Only Malta has a PIT */
182 setup_pit_timer();
183#endif
184
185 plat_perf_setup();
186}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 08:25:42 -0500