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-rw-r--r--arch/mips/mips-boards/generic/time.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 4fab3b2e8736..1d00b778ff1e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -134,7 +134,7 @@ void __init plat_time_init(void)
134 /* Set Data mode - binary. */ 134 /* Set Data mode - binary. */
135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
136 136
137 est_freq = estimate_cpu_frequency (); 137 est_freq = estimate_cpu_frequency();
138 138
139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
140 (est_freq%1000000)*100/1000000); 140 (est_freq%1000000)*100/1000000);
@@ -166,7 +166,7 @@ void __init plat_perf_setup(void)
166 166
167#ifdef MSC01E_INT_BASE 167#ifdef MSC01E_INT_BASE
168 if (cpu_has_veic) { 168 if (cpu_has_veic) {
169 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); 169 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
171 } else 171 } else
172#endif 172#endif
@@ -183,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
183{ 183{
184#ifdef MSC01E_INT_BASE 184#ifdef MSC01E_INT_BASE
185 if (cpu_has_veic) { 185 if (cpu_has_veic) {
186 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); 186 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
188 } 188 }
189 else 189 else