diff options
Diffstat (limited to 'arch/mips/mips-boards/generic/time.c')
-rw-r--r-- | arch/mips/mips-boards/generic/time.c | 50 |
1 files changed, 16 insertions, 34 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 8f1000f51b3d..c45d556aa96b 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c | |||
@@ -54,7 +54,7 @@ | |||
54 | unsigned long cpu_khz; | 54 | unsigned long cpu_khz; |
55 | 55 | ||
56 | static int mips_cpu_timer_irq; | 56 | static int mips_cpu_timer_irq; |
57 | extern int mipsxx_perfcount_irq; | 57 | extern int cp0_perfcount_irq; |
58 | extern void smtc_timer_broadcast(int); | 58 | extern void smtc_timer_broadcast(int); |
59 | 59 | ||
60 | static void mips_timer_dispatch(void) | 60 | static void mips_timer_dispatch(void) |
@@ -64,7 +64,7 @@ static void mips_timer_dispatch(void) | |||
64 | 64 | ||
65 | static void mips_perf_dispatch(void) | 65 | static void mips_perf_dispatch(void) |
66 | { | 66 | { |
67 | do_IRQ(mipsxx_perfcount_irq); | 67 | do_IRQ(cp0_perfcount_irq); |
68 | } | 68 | } |
69 | 69 | ||
70 | /* | 70 | /* |
@@ -82,12 +82,12 @@ static inline int handle_perf_irq (int r2) | |||
82 | { | 82 | { |
83 | /* | 83 | /* |
84 | * The performance counter overflow interrupt may be shared with the | 84 | * The performance counter overflow interrupt may be shared with the |
85 | * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a | 85 | * timer interrupt (cp0_perfcount_irq < 0). If it is and a |
86 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) | 86 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) |
87 | * and we can't reliably determine if a counter interrupt has also | 87 | * and we can't reliably determine if a counter interrupt has also |
88 | * happened (!r2) then don't check for a timer interrupt. | 88 | * happened (!r2) then don't check for a timer interrupt. |
89 | */ | 89 | */ |
90 | return (mipsxx_perfcount_irq < 0) && | 90 | return (cp0_perfcount_irq < 0) && |
91 | perf_irq() == IRQ_HANDLED && | 91 | perf_irq() == IRQ_HANDLED && |
92 | !r2; | 92 | !r2; |
93 | } | 93 | } |
@@ -259,42 +259,31 @@ static struct irqaction perf_irqaction = { | |||
259 | 259 | ||
260 | void __init plat_perf_setup(struct irqaction *irq) | 260 | void __init plat_perf_setup(struct irqaction *irq) |
261 | { | 261 | { |
262 | int hwint = 0; | 262 | cp0_perfcount_irq = -1; |
263 | mipsxx_perfcount_irq = -1; | ||
264 | 263 | ||
265 | #ifdef MSC01E_INT_BASE | 264 | #ifdef MSC01E_INT_BASE |
266 | if (cpu_has_veic) { | 265 | if (cpu_has_veic) { |
267 | set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); | 266 | set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); |
268 | mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; | 267 | cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
269 | } else | 268 | } else |
270 | #endif | 269 | #endif |
271 | if (cpu_has_mips_r2) { | 270 | if (cp0_perfcount_irq >= 0) { |
272 | /* | 271 | if (cpu_has_vint) |
273 | * Read IntCtl.IPPCI to determine the performance | 272 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); |
274 | * counter interrupt | ||
275 | */ | ||
276 | hwint = (read_c0_intctl () >> 26) & 7; | ||
277 | if (hwint != MIPSCPU_INT_CPUCTR) { | ||
278 | if (cpu_has_vint) | ||
279 | set_vi_handler (hwint, mips_perf_dispatch); | ||
280 | mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint; | ||
281 | } | ||
282 | } | ||
283 | if (mipsxx_perfcount_irq >= 0) { | ||
284 | #ifdef CONFIG_MIPS_MT_SMTC | 273 | #ifdef CONFIG_MIPS_MT_SMTC |
285 | setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint); | 274 | setup_irq_smtc(cp0_perfcount_irq, irq, |
275 | 0x100 << cp0_perfcount_irq); | ||
286 | #else | 276 | #else |
287 | setup_irq(mipsxx_perfcount_irq, irq); | 277 | setup_irq(cp0_perfcount_irq, irq); |
288 | #endif /* CONFIG_MIPS_MT_SMTC */ | 278 | #endif /* CONFIG_MIPS_MT_SMTC */ |
289 | #ifdef CONFIG_SMP | 279 | #ifdef CONFIG_SMP |
290 | set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq); | 280 | set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); |
291 | #endif | 281 | #endif |
292 | } | 282 | } |
293 | } | 283 | } |
294 | 284 | ||
295 | void __init plat_timer_setup(struct irqaction *irq) | 285 | void __init plat_timer_setup(struct irqaction *irq) |
296 | { | 286 | { |
297 | int hwint = 0; | ||
298 | #ifdef MSC01E_INT_BASE | 287 | #ifdef MSC01E_INT_BASE |
299 | if (cpu_has_veic) { | 288 | if (cpu_has_veic) { |
300 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); | 289 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); |
@@ -303,22 +292,15 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
303 | else | 292 | else |
304 | #endif | 293 | #endif |
305 | { | 294 | { |
306 | if (cpu_has_mips_r2) | ||
307 | /* | ||
308 | * Read IntCtl.IPTI to determine the timer interrupt | ||
309 | */ | ||
310 | hwint = (read_c0_intctl () >> 29) & 7; | ||
311 | else | ||
312 | hwint = MIPSCPU_INT_CPUCTR; | ||
313 | if (cpu_has_vint) | 295 | if (cpu_has_vint) |
314 | set_vi_handler (hwint, mips_timer_dispatch); | 296 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
315 | mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint; | 297 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
316 | } | 298 | } |
317 | 299 | ||
318 | /* we are using the cpu counter for timer interrupts */ | 300 | /* we are using the cpu counter for timer interrupts */ |
319 | irq->handler = mips_timer_interrupt; /* we use our own handler */ | 301 | irq->handler = mips_timer_interrupt; /* we use our own handler */ |
320 | #ifdef CONFIG_MIPS_MT_SMTC | 302 | #ifdef CONFIG_MIPS_MT_SMTC |
321 | setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint); | 303 | setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); |
322 | #else | 304 | #else |
323 | setup_irq(mips_cpu_timer_irq, irq); | 305 | setup_irq(mips_cpu_timer_irq, irq); |
324 | #endif /* CONFIG_MIPS_MT_SMTC */ | 306 | #endif /* CONFIG_MIPS_MT_SMTC */ |