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-rw-r--r--arch/mips/mips-boards/generic/time.c23
1 files changed, 11 insertions, 12 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 8d15861fce61..6f8a9fe7c1e3 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -30,7 +30,6 @@
30 30
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h> 32#include <asm/mipsmtregs.h>
33#include <asm/ptrace.h>
34#include <asm/hardirq.h> 33#include <asm/hardirq.h>
35#include <asm/irq.h> 34#include <asm/irq.h>
36#include <asm/div64.h> 35#include <asm/div64.h>
@@ -82,19 +81,19 @@ static inline void scroll_display_message(void)
82 } 81 }
83} 82}
84 83
85static void mips_timer_dispatch (struct pt_regs *regs) 84static void mips_timer_dispatch(void)
86{ 85{
87 do_IRQ (mips_cpu_timer_irq, regs); 86 do_IRQ(mips_cpu_timer_irq);
88} 87}
89 88
90/* 89/*
91 * Redeclare until I get around mopping the timer code insanity on MIPS. 90 * Redeclare until I get around mopping the timer code insanity on MIPS.
92 */ 91 */
93extern int null_perf_irq(struct pt_regs *regs); 92extern int null_perf_irq(void);
94 93
95extern int (*perf_irq)(struct pt_regs *regs); 94extern int (*perf_irq)(void);
96 95
97irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 96irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
98{ 97{
99 int cpu = smp_processor_id(); 98 int cpu = smp_processor_id();
100 99
@@ -119,7 +118,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
119 * perf counter overflow, or both. 118 * perf counter overflow, or both.
120 */ 119 */
121 if (read_c0_cause() & (1 << 26)) 120 if (read_c0_cause() & (1 << 26))
122 perf_irq(regs); 121 perf_irq();
123 122
124 if (read_c0_cause() & (1 << 30)) { 123 if (read_c0_cause() & (1 << 30)) {
125 /* If timer interrupt, make it de-assert */ 124 /* If timer interrupt, make it de-assert */
@@ -139,13 +138,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
139 * the tick on VPE 0 to run the full timer_interrupt(). 138 * the tick on VPE 0 to run the full timer_interrupt().
140 */ 139 */
141 if (cpu_data[cpu].vpe_id == 0) { 140 if (cpu_data[cpu].vpe_id == 0) {
142 timer_interrupt(irq, NULL, regs); 141 timer_interrupt(irq, NULL);
143 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 142 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
144 scroll_display_message(); 143 scroll_display_message();
145 } else { 144 } else {
146 write_c0_compare(read_c0_count() + 145 write_c0_compare(read_c0_count() +
147 (mips_hpt_frequency/HZ)); 146 (mips_hpt_frequency/HZ));
148 local_timer_interrupt(irq, dev_id, regs); 147 local_timer_interrupt(irq, dev_id);
149 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 148 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
150 } 149 }
151 } 150 }
@@ -159,12 +158,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
159 * timer int. 158 * timer int.
160 */ 159 */
161 if (!r2 || (read_c0_cause() & (1 << 26))) 160 if (!r2 || (read_c0_cause() & (1 << 26)))
162 if (perf_irq(regs)) 161 if (perf_irq())
163 goto out; 162 goto out;
164 163
165 /* we keep interrupt disabled all the time */ 164 /* we keep interrupt disabled all the time */
166 if (!r2 || (read_c0_cause() & (1 << 30))) 165 if (!r2 || (read_c0_cause() & (1 << 30)))
167 timer_interrupt(irq, NULL, regs); 166 timer_interrupt(irq, NULL);
168 167
169 scroll_display_message(); 168 scroll_display_message();
170 } else { 169 } else {
@@ -180,7 +179,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
180 /* 179 /*
181 * Other CPUs should do profiling and process accounting 180 * Other CPUs should do profiling and process accounting
182 */ 181 */
183 local_timer_interrupt(irq, dev_id, regs); 182 local_timer_interrupt(irq, dev_id);
184 } 183 }
185out: 184out:
186#endif /* CONFIG_MIPS_MT_SMTC */ 185#endif /* CONFIG_MIPS_MT_SMTC */