diff options
Diffstat (limited to 'arch/mips/mips-boards/generic/time.c')
-rw-r--r-- | arch/mips/mips-boards/generic/time.c | 49 |
1 files changed, 32 insertions, 17 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 16315444dd5a..3a6f1428b2cb 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c | |||
@@ -31,22 +31,21 @@ | |||
31 | 31 | ||
32 | #include <asm/mipsregs.h> | 32 | #include <asm/mipsregs.h> |
33 | #include <asm/ptrace.h> | 33 | #include <asm/ptrace.h> |
34 | #include <asm/hardirq.h> | ||
35 | #include <asm/irq.h> | ||
34 | #include <asm/div64.h> | 36 | #include <asm/div64.h> |
35 | #include <asm/cpu.h> | 37 | #include <asm/cpu.h> |
36 | #include <asm/time.h> | 38 | #include <asm/time.h> |
37 | #include <asm/mc146818-time.h> | 39 | #include <asm/mc146818-time.h> |
40 | #include <asm/msc01_ic.h> | ||
38 | 41 | ||
39 | #include <asm/mips-boards/generic.h> | 42 | #include <asm/mips-boards/generic.h> |
40 | #include <asm/mips-boards/prom.h> | 43 | #include <asm/mips-boards/prom.h> |
44 | #include <asm/mips-boards/maltaint.h> | ||
45 | #include <asm/mc146818-time.h> | ||
41 | 46 | ||
42 | unsigned long cpu_khz; | 47 | unsigned long cpu_khz; |
43 | 48 | ||
44 | #if defined(CONFIG_MIPS_SEAD) | ||
45 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5) | ||
46 | #else | ||
47 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | ||
48 | #endif | ||
49 | |||
50 | #if defined(CONFIG_MIPS_ATLAS) | 49 | #if defined(CONFIG_MIPS_ATLAS) |
51 | static char display_string[] = " LINUX ON ATLAS "; | 50 | static char display_string[] = " LINUX ON ATLAS "; |
52 | #endif | 51 | #endif |
@@ -59,20 +58,27 @@ static char display_string[] = " LINUX ON SEAD "; | |||
59 | static unsigned int display_count = 0; | 58 | static unsigned int display_count = 0; |
60 | #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) | 59 | #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) |
61 | 60 | ||
62 | #define MIPS_CPU_TIMER_IRQ (NR_IRQS-1) | ||
63 | |||
64 | static unsigned int timer_tick_count=0; | 61 | static unsigned int timer_tick_count=0; |
62 | static int mips_cpu_timer_irq; | ||
65 | 63 | ||
66 | void mips_timer_interrupt(struct pt_regs *regs) | 64 | static void mips_timer_dispatch (struct pt_regs *regs) |
67 | { | 65 | { |
66 | do_IRQ (mips_cpu_timer_irq, regs); | ||
67 | } | ||
68 | |||
69 | irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
70 | { | ||
71 | irqreturn_t r; | ||
72 | |||
73 | r = timer_interrupt(irq, dev_id, regs); | ||
74 | |||
68 | if ((timer_tick_count++ % HZ) == 0) { | 75 | if ((timer_tick_count++ % HZ) == 0) { |
69 | mips_display_message(&display_string[display_count++]); | 76 | mips_display_message(&display_string[display_count++]); |
70 | if (display_count == MAX_DISPLAY_COUNT) | 77 | if (display_count == MAX_DISPLAY_COUNT) |
71 | display_count = 0; | 78 | display_count = 0; |
72 | |||
73 | } | 79 | } |
74 | 80 | ||
75 | ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); | 81 | return r; |
76 | } | 82 | } |
77 | 83 | ||
78 | /* | 84 | /* |
@@ -140,10 +146,8 @@ void __init mips_time_init(void) | |||
140 | 146 | ||
141 | local_irq_save(flags); | 147 | local_irq_save(flags); |
142 | 148 | ||
143 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) | ||
144 | /* Set Data mode - binary. */ | 149 | /* Set Data mode - binary. */ |
145 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | 150 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); |
146 | #endif | ||
147 | 151 | ||
148 | est_freq = estimate_cpu_frequency (); | 152 | est_freq = estimate_cpu_frequency (); |
149 | 153 | ||
@@ -157,11 +161,22 @@ void __init mips_time_init(void) | |||
157 | 161 | ||
158 | void __init mips_timer_setup(struct irqaction *irq) | 162 | void __init mips_timer_setup(struct irqaction *irq) |
159 | { | 163 | { |
164 | if (cpu_has_veic) { | ||
165 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); | ||
166 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | ||
167 | } | ||
168 | else { | ||
169 | if (cpu_has_vint) | ||
170 | set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); | ||
171 | mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; | ||
172 | } | ||
173 | |||
174 | |||
160 | /* we are using the cpu counter for timer interrupts */ | 175 | /* we are using the cpu counter for timer interrupts */ |
161 | irq->handler = no_action; /* we use our own handler */ | 176 | irq->handler = mips_timer_interrupt; /* we use our own handler */ |
162 | setup_irq(MIPS_CPU_TIMER_IRQ, irq); | 177 | setup_irq(mips_cpu_timer_irq, irq); |
178 | |||
163 | 179 | ||
164 | /* to generate the first timer interrupt */ | 180 | /* to generate the first timer interrupt */ |
165 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); | 181 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); |
166 | set_c0_status(ALLINTS); | ||
167 | } | 182 | } |