aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mips-boards/generic/init.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/mips-boards/generic/init.c')
-rw-r--r--arch/mips/mips-boards/generic/init.c61
1 files changed, 40 insertions, 21 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 311155d1d3ed..d821b13d24a0 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -22,18 +24,17 @@
22#include <linux/string.h> 24#include <linux/string.h>
23#include <linux/kernel.h> 25#include <linux/kernel.h>
24 26
25#include <asm/io.h>
26#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/gt64120.h>
29#include <asm/io.h>
30#include <asm/system.h>
31
27#include <asm/mips-boards/prom.h> 32#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/generic.h> 33#include <asm/mips-boards/generic.h>
29#ifdef CONFIG_MIPS_GT64120
30#include <asm/gt64120.h>
31#endif
32#include <asm/mips-boards/msc01_pci.h>
33#include <asm/mips-boards/bonito64.h> 34#include <asm/mips-boards/bonito64.h>
34#ifdef CONFIG_MIPS_MALTA 35#include <asm/mips-boards/msc01_pci.h>
36
35#include <asm/mips-boards/malta.h> 37#include <asm/mips-boards/malta.h>
36#endif
37 38
38#ifdef CONFIG_KGDB 39#ifdef CONFIG_KGDB
39extern int rs_kgdb_hook(int, int); 40extern int rs_kgdb_hook(int, int);
@@ -225,6 +226,8 @@ void __init kgdb_config (void)
225 226
226void __init prom_init(void) 227void __init prom_init(void)
227{ 228{
229 u32 start, map, mask, data;
230
228 prom_argc = fw_arg0; 231 prom_argc = fw_arg0;
229 _prom_argv = (int *) fw_arg1; 232 _prom_argv = (int *) fw_arg1;
230 _prom_envp = (int *) fw_arg2; 233 _prom_envp = (int *) fw_arg2;
@@ -266,12 +269,15 @@ void __init prom_init(void)
266#else 269#else
267 GT_WRITE(GT_PCI0_CMD_OFS, 0); 270 GT_WRITE(GT_PCI0_CMD_OFS, 0);
268#endif 271#endif
272 /* Fix up PCI I/O mapping if necessary (for Atlas). */
273 start = GT_READ(GT_PCI0IOLD_OFS);
274 map = GT_READ(GT_PCI0IOREMAP_OFS);
275 if ((start & map) != 0) {
276 map &= ~start;
277 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
278 }
269 279
270#ifdef CONFIG_MIPS_MALTA
271 set_io_port_base(MALTA_GT_PORT_BASE); 280 set_io_port_base(MALTA_GT_PORT_BASE);
272#else
273 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
274#endif
275 break; 281 break;
276 282
277 case MIPS_REVISION_CORID_CORE_EMUL_BON: 283 case MIPS_REVISION_CORID_CORE_EMUL_BON:
@@ -300,11 +306,7 @@ void __init prom_init(void)
300 BONITO_BONGENCFG_BYTESWAP; 306 BONITO_BONGENCFG_BYTESWAP;
301#endif 307#endif
302 308
303#ifdef CONFIG_MIPS_MALTA
304 set_io_port_base(MALTA_BONITO_PORT_BASE); 309 set_io_port_base(MALTA_BONITO_PORT_BASE);
305#else
306 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
307#endif
308 break; 310 break;
309 311
310 case MIPS_REVISION_CORID_CORE_MSC: 312 case MIPS_REVISION_CORID_CORE_MSC:
@@ -312,6 +314,12 @@ void __init prom_init(void)
312 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 314 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 315 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
314 316
317 mb();
318 MSC_READ(MSC01_PCI_CFG, data);
319 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
320 wmb();
321
322 /* Fix up lane swapping. */
315#ifdef CONFIG_CPU_LITTLE_ENDIAN 323#ifdef CONFIG_CPU_LITTLE_ENDIAN
316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 324 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
317#else 325#else
@@ -320,12 +328,23 @@ void __init prom_init(void)
320 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 328 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
321 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 329 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
322#endif 330#endif
331 /* Fix up target memory mapping. */
332 MSC_READ(MSC01_PCI_BAR0, mask);
333 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
334
335 /* Don't handle target retries indefinitely. */
336 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
337 MSC01_PCI_CFG_MAXRTRY_MSK)
338 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
339 MSC01_PCI_CFG_MAXRTRY_SHF)) |
340 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
341 MSC01_PCI_CFG_MAXRTRY_SHF);
342
343 wmb();
344 MSC_WRITE(MSC01_PCI_CFG, data);
345 mb();
323 346
324#ifdef CONFIG_MIPS_MALTA
325 set_io_port_base(MALTA_MSC_PORT_BASE); 347 set_io_port_base(MALTA_MSC_PORT_BASE);
326#else
327 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
328#endif
329 break; 348 break;
330 349
331 default: 350 default: