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-rw-r--r--arch/mips/math-emu/cp1emu.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 8f2f8e9d8b21..f2338d1c0b48 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -78,6 +78,9 @@ DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
78#define FPCREG_RID 0 /* $0 = revision id */ 78#define FPCREG_RID 0 /* $0 = revision id */
79#define FPCREG_CSR 31 /* $31 = csr */ 79#define FPCREG_CSR 31 /* $31 = csr */
80 80
81/* Determine rounding mode from the RM bits of the FCSR */
82#define modeindex(v) ((v) & FPU_CSR_RM)
83
81/* Convert Mips rounding mode (0..3) to IEEE library modes. */ 84/* Convert Mips rounding mode (0..3) to IEEE library modes. */
82static const unsigned char ieee_rm[4] = { 85static const unsigned char ieee_rm[4] = {
83 [FPU_CSR_RN] = IEEE754_RN, 86 [FPU_CSR_RN] = IEEE754_RN,
@@ -384,10 +387,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
384 (void *) (xcp->cp0_epc), 387 (void *) (xcp->cp0_epc),
385 MIPSInst_RT(ir), value); 388 MIPSInst_RT(ir), value);
386#endif 389#endif
387 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 390
388 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 391 /*
389 /* convert to ieee library modes */ 392 * Don't write reserved bits,
390 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; 393 * and convert to ieee library modes
394 */
395 ctx->fcr31 = (value &
396 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
397 ieee_rm[modeindex(value)];
391 } 398 }
392 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 399 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
393 return SIGFPE; 400 return SIGFPE;