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-rw-r--r--arch/mips/math-emu/dsemul.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index aa989c2246da..8079f3d1eca0 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -28,9 +28,6 @@
28#endif 28#endif
29#define __mips 4 29#define __mips 4
30 30
31extern struct mips_fpu_emulator_private fpuemuprivate;
32
33
34/* 31/*
35 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 32 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
36 * we have to emulate the instruction in a COP1 branch delay slot. Do 33 * we have to emulate the instruction in a COP1 branch delay slot. Do
@@ -52,10 +49,10 @@ struct emuframe {
52 mips_instruction emul; 49 mips_instruction emul;
53 mips_instruction badinst; 50 mips_instruction badinst;
54 mips_instruction cookie; 51 mips_instruction cookie;
55 gpreg_t epc; 52 unsigned long epc;
56}; 53};
57 54
58int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) 55int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
59{ 56{
60 extern asmlinkage void handle_dsemulret(void); 57 extern asmlinkage void handle_dsemulret(void);
61 mips_instruction *dsemul_insns; 58 mips_instruction *dsemul_insns;
@@ -91,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
91 */ 88 */
92 89
93 /* Ensure that the two instructions are in the same cache line */ 90 /* Ensure that the two instructions are in the same cache line */
94 dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 91 dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
95 fr = (struct emuframe *) dsemul_insns; 92 fr = (struct emuframe *) dsemul_insns;
96 93
97 /* Verify that the stack pointer is not competely insane */ 94 /* Verify that the stack pointer is not competely insane */
@@ -104,11 +101,11 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
104 err |= __put_user(cpc, &fr->epc); 101 err |= __put_user(cpc, &fr->epc);
105 102
106 if (unlikely(err)) { 103 if (unlikely(err)) {
107 fpuemuprivate.stats.errors++; 104 fpuemustats.errors++;
108 return SIGBUS; 105 return SIGBUS;
109 } 106 }
110 107
111 regs->cp0_epc = VA_TO_REG & fr->emul; 108 regs->cp0_epc = (unsigned long) &fr->emul;
112 109
113 flush_cache_sigtramp((unsigned long)&fr->badinst); 110 flush_cache_sigtramp((unsigned long)&fr->badinst);
114 111
@@ -118,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
118int do_dsemulret(struct pt_regs *xcp) 115int do_dsemulret(struct pt_regs *xcp)
119{ 116{
120 struct emuframe *fr; 117 struct emuframe *fr;
121 gpreg_t epc; 118 unsigned long epc;
122 u32 insn, cookie; 119 u32 insn, cookie;
123 int err = 0; 120 int err = 0;
124 121
@@ -141,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp)
141 err |= __get_user(cookie, &fr->cookie); 138 err |= __get_user(cookie, &fr->cookie);
142 139
143 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { 140 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
144 fpuemuprivate.stats.errors++; 141 fpuemustats.errors++;
145 return 0; 142 return 0;
146 } 143 }
147 144