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Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r--arch/mips/math-emu/cp1emu.c229
1 files changed, 94 insertions, 135 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 99c550632d44..aa5818a0d884 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *,
70 70
71/* Further private data for which no space exists in mips_fpu_soft_struct */ 71/* Further private data for which no space exists in mips_fpu_soft_struct */
72 72
73struct mips_fpu_emulator_private fpuemuprivate; 73struct mips_fpu_emulator_stats fpuemustats;
74 74
75/* Control registers */ 75/* Control registers */
76 76
@@ -79,7 +79,17 @@ struct mips_fpu_emulator_private fpuemuprivate;
79 79
80/* Convert Mips rounding mode (0..3) to IEEE library modes. */ 80/* Convert Mips rounding mode (0..3) to IEEE library modes. */
81static const unsigned char ieee_rm[4] = { 81static const unsigned char ieee_rm[4] = {
82 IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD 82 [FPU_CSR_RN] = IEEE754_RN,
83 [FPU_CSR_RZ] = IEEE754_RZ,
84 [FPU_CSR_RU] = IEEE754_RU,
85 [FPU_CSR_RD] = IEEE754_RD,
86};
87/* Convert IEEE library modes to Mips rounding mode (0..3). */
88static const unsigned char mips_rm[4] = {
89 [IEEE754_RN] = FPU_CSR_RN,
90 [IEEE754_RZ] = FPU_CSR_RZ,
91 [IEEE754_RD] = FPU_CSR_RD,
92 [IEEE754_RU] = FPU_CSR_RU,
83}; 93};
84 94
85#if __mips >= 4 95#if __mips >= 4
@@ -196,11 +206,11 @@ static int isBranchInstr(mips_instruction * i)
196static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) 206static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
197{ 207{
198 mips_instruction ir; 208 mips_instruction ir;
199 vaddr_t emulpc, contpc; 209 void * emulpc, *contpc;
200 unsigned int cond; 210 unsigned int cond;
201 211
202 if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { 212 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
203 fpuemuprivate.stats.errors++; 213 fpuemustats.errors++;
204 return SIGBUS; 214 return SIGBUS;
205 } 215 }
206 216
@@ -221,41 +231,39 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
221 * Linux MIPS branch emulator operates on context, updating the 231 * Linux MIPS branch emulator operates on context, updating the
222 * cp0_epc. 232 * cp0_epc.
223 */ 233 */
224 emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ 234 emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
225 235
226 if (__compute_return_epc(xcp)) { 236 if (__compute_return_epc(xcp)) {
227#ifdef CP1DBG 237#ifdef CP1DBG
228 printk("failed to emulate branch at %p\n", 238 printk("failed to emulate branch at %p\n",
229 REG_TO_VA(xcp->cp0_epc)); 239 (void *) (xcp->cp0_epc));
230#endif 240#endif
231 return SIGILL; 241 return SIGILL;
232 } 242 }
233 if (get_user(ir, (mips_instruction *) emulpc)) { 243 if (get_user(ir, (mips_instruction __user *) emulpc)) {
234 fpuemuprivate.stats.errors++; 244 fpuemustats.errors++;
235 return SIGBUS; 245 return SIGBUS;
236 } 246 }
237 /* __compute_return_epc() will have updated cp0_epc */ 247 /* __compute_return_epc() will have updated cp0_epc */
238 contpc = REG_TO_VA xcp->cp0_epc; 248 contpc = (void *) xcp->cp0_epc;
239 /* In order not to confuse ptrace() et al, tweak context */ 249 /* In order not to confuse ptrace() et al, tweak context */
240 xcp->cp0_epc = VA_TO_REG emulpc - 4; 250 xcp->cp0_epc = (unsigned long) emulpc - 4;
241 } 251 } else {
242 else { 252 emulpc = (void *) xcp->cp0_epc;
243 emulpc = REG_TO_VA xcp->cp0_epc; 253 contpc = (void *) (xcp->cp0_epc + 4);
244 contpc = REG_TO_VA(xcp->cp0_epc + 4);
245 } 254 }
246 255
247 emul: 256 emul:
248 fpuemuprivate.stats.emulated++; 257 fpuemustats.emulated++;
249 switch (MIPSInst_OPCODE(ir)) { 258 switch (MIPSInst_OPCODE(ir)) {
250#ifndef SINGLE_ONLY_FPU
251 case ldc1_op:{ 259 case ldc1_op:{
252 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 260 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
253 MIPSInst_SIMM(ir)); 261 MIPSInst_SIMM(ir));
254 u64 val; 262 u64 val;
255 263
256 fpuemuprivate.stats.loads++; 264 fpuemustats.loads++;
257 if (get_user(val, va)) { 265 if (get_user(val, va)) {
258 fpuemuprivate.stats.errors++; 266 fpuemustats.errors++;
259 return SIGBUS; 267 return SIGBUS;
260 } 268 }
261 DITOREG(val, MIPSInst_RT(ir)); 269 DITOREG(val, MIPSInst_RT(ir));
@@ -263,55 +271,42 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
263 } 271 }
264 272
265 case sdc1_op:{ 273 case sdc1_op:{
266 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 274 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
267 MIPSInst_SIMM(ir)); 275 MIPSInst_SIMM(ir));
268 u64 val; 276 u64 val;
269 277
270 fpuemuprivate.stats.stores++; 278 fpuemustats.stores++;
271 DIFROMREG(val, MIPSInst_RT(ir)); 279 DIFROMREG(val, MIPSInst_RT(ir));
272 if (put_user(val, va)) { 280 if (put_user(val, va)) {
273 fpuemuprivate.stats.errors++; 281 fpuemustats.errors++;
274 return SIGBUS; 282 return SIGBUS;
275 } 283 }
276 break; 284 break;
277 } 285 }
278#endif
279 286
280 case lwc1_op:{ 287 case lwc1_op:{
281 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 288 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
282 MIPSInst_SIMM(ir)); 289 MIPSInst_SIMM(ir));
283 u32 val; 290 u32 val;
284 291
285 fpuemuprivate.stats.loads++; 292 fpuemustats.loads++;
286 if (get_user(val, va)) { 293 if (get_user(val, va)) {
287 fpuemuprivate.stats.errors++; 294 fpuemustats.errors++;
288 return SIGBUS; 295 return SIGBUS;
289 } 296 }
290#ifdef SINGLE_ONLY_FPU
291 if (MIPSInst_RT(ir) & 1) {
292 /* illegal register in single-float mode */
293 return SIGILL;
294 }
295#endif
296 SITOREG(val, MIPSInst_RT(ir)); 297 SITOREG(val, MIPSInst_RT(ir));
297 break; 298 break;
298 } 299 }
299 300
300 case swc1_op:{ 301 case swc1_op:{
301 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 302 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
302 MIPSInst_SIMM(ir)); 303 MIPSInst_SIMM(ir));
303 u32 val; 304 u32 val;
304 305
305 fpuemuprivate.stats.stores++; 306 fpuemustats.stores++;
306#ifdef SINGLE_ONLY_FPU
307 if (MIPSInst_RT(ir) & 1) {
308 /* illegal register in single-float mode */
309 return SIGILL;
310 }
311#endif
312 SIFROMREG(val, MIPSInst_RT(ir)); 307 SIFROMREG(val, MIPSInst_RT(ir));
313 if (put_user(val, va)) { 308 if (put_user(val, va)) {
314 fpuemuprivate.stats.errors++; 309 fpuemustats.errors++;
315 return SIGBUS; 310 return SIGBUS;
316 } 311 }
317 break; 312 break;
@@ -320,7 +315,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
320 case cop1_op: 315 case cop1_op:
321 switch (MIPSInst_RS(ir)) { 316 switch (MIPSInst_RS(ir)) {
322 317
323#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 318#if defined(__mips64)
324 case dmfc_op: 319 case dmfc_op:
325 /* copregister fs -> gpr[rt] */ 320 /* copregister fs -> gpr[rt] */
326 if (MIPSInst_RT(ir) != 0) { 321 if (MIPSInst_RT(ir) != 0) {
@@ -337,12 +332,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
337 332
338 case mfc_op: 333 case mfc_op:
339 /* copregister rd -> gpr[rt] */ 334 /* copregister rd -> gpr[rt] */
340#ifdef SINGLE_ONLY_FPU
341 if (MIPSInst_RD(ir) & 1) {
342 /* illegal register in single-float mode */
343 return SIGILL;
344 }
345#endif
346 if (MIPSInst_RT(ir) != 0) { 335 if (MIPSInst_RT(ir) != 0) {
347 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 336 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
348 MIPSInst_RD(ir)); 337 MIPSInst_RD(ir));
@@ -351,12 +340,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
351 340
352 case mtc_op: 341 case mtc_op:
353 /* copregister rd <- rt */ 342 /* copregister rd <- rt */
354#ifdef SINGLE_ONLY_FPU
355 if (MIPSInst_RD(ir) & 1) {
356 /* illegal register in single-float mode */
357 return SIGILL;
358 }
359#endif
360 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 343 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
361 break; 344 break;
362 345
@@ -369,9 +352,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
369 } 352 }
370 if (MIPSInst_RD(ir) == FPCREG_CSR) { 353 if (MIPSInst_RD(ir) == FPCREG_CSR) {
371 value = ctx->fcr31; 354 value = ctx->fcr31;
355 value = (value & ~0x3) | mips_rm[value & 0x3];
372#ifdef CSRTRACE 356#ifdef CSRTRACE
373 printk("%p gpr[%d]<-csr=%08x\n", 357 printk("%p gpr[%d]<-csr=%08x\n",
374 REG_TO_VA(xcp->cp0_epc), 358 (void *) (xcp->cp0_epc),
375 MIPSInst_RT(ir), value); 359 MIPSInst_RT(ir), value);
376#endif 360#endif
377 } 361 }
@@ -398,14 +382,13 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
398 if (MIPSInst_RD(ir) == FPCREG_CSR) { 382 if (MIPSInst_RD(ir) == FPCREG_CSR) {
399#ifdef CSRTRACE 383#ifdef CSRTRACE
400 printk("%p gpr[%d]->csr=%08x\n", 384 printk("%p gpr[%d]->csr=%08x\n",
401 REG_TO_VA(xcp->cp0_epc), 385 (void *) (xcp->cp0_epc),
402 MIPSInst_RT(ir), value); 386 MIPSInst_RT(ir), value);
403#endif 387#endif
404 ctx->fcr31 = value; 388 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
405 /* copy new rounding mode and 389 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
406 flush bit to ieee library state! */ 390 /* convert to ieee library modes */
407 ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; 391 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
408 ieee754_csr.rm = ieee_rm[value & 0x3];
409 } 392 }
410 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 393 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
411 return SIGFPE; 394 return SIGFPE;
@@ -445,20 +428,20 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
445 * instruction 428 * instruction
446 */ 429 */
447 xcp->cp0_epc += 4; 430 xcp->cp0_epc += 4;
448 contpc = REG_TO_VA 431 contpc = (void *)
449 (xcp->cp0_epc + 432 (xcp->cp0_epc +
450 (MIPSInst_SIMM(ir) << 2)); 433 (MIPSInst_SIMM(ir) << 2));
451 434
452 if (get_user(ir, (mips_instruction *) 435 if (get_user(ir,
453 REG_TO_VA xcp->cp0_epc)) { 436 (mips_instruction __user *) xcp->cp0_epc)) {
454 fpuemuprivate.stats.errors++; 437 fpuemustats.errors++;
455 return SIGBUS; 438 return SIGBUS;
456 } 439 }
457 440
458 switch (MIPSInst_OPCODE(ir)) { 441 switch (MIPSInst_OPCODE(ir)) {
459 case lwc1_op: 442 case lwc1_op:
460 case swc1_op: 443 case swc1_op:
461#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU) 444#if (__mips >= 2 || defined(__mips64))
462 case ldc1_op: 445 case ldc1_op:
463 case sdc1_op: 446 case sdc1_op:
464#endif 447#endif
@@ -480,7 +463,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
480 * Single step the non-cp1 463 * Single step the non-cp1
481 * instruction in the dslot 464 * instruction in the dslot
482 */ 465 */
483 return mips_dsemul(xcp, ir, VA_TO_REG contpc); 466 return mips_dsemul(xcp, ir, (unsigned long) contpc);
484 } 467 }
485 else { 468 else {
486 /* branch not taken */ 469 /* branch not taken */
@@ -539,8 +522,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
539 } 522 }
540 523
541 /* we did it !! */ 524 /* we did it !! */
542 xcp->cp0_epc = VA_TO_REG(contpc); 525 xcp->cp0_epc = (unsigned long) contpc;
543 xcp->cp0_cause &= ~CAUSEF_BD; 526 xcp->cp0_cause &= ~CAUSEF_BD;
527
544 return 0; 528 return 0;
545} 529}
546 530
@@ -570,7 +554,7 @@ static const unsigned char cmptab[8] = {
570static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ 554static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
571 ieee754##p t) \ 555 ieee754##p t) \
572{ \ 556{ \
573 struct ieee754_csr ieee754_csr_save; \ 557 struct _ieee754_csr ieee754_csr_save; \
574 s = f1 (s, t); \ 558 s = f1 (s, t); \
575 ieee754_csr_save = ieee754_csr; \ 559 ieee754_csr_save = ieee754_csr; \
576 s = f2 (s, r); \ 560 s = f2 (s, r); \
@@ -616,54 +600,38 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
616{ 600{
617 unsigned rcsr = 0; /* resulting csr */ 601 unsigned rcsr = 0; /* resulting csr */
618 602
619 fpuemuprivate.stats.cp1xops++; 603 fpuemustats.cp1xops++;
620 604
621 switch (MIPSInst_FMA_FFMT(ir)) { 605 switch (MIPSInst_FMA_FFMT(ir)) {
622 case s_fmt:{ /* 0 */ 606 case s_fmt:{ /* 0 */
623 607
624 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); 608 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
625 ieee754sp fd, fr, fs, ft; 609 ieee754sp fd, fr, fs, ft;
626 u32 *va; 610 u32 __user *va;
627 u32 val; 611 u32 val;
628 612
629 switch (MIPSInst_FUNC(ir)) { 613 switch (MIPSInst_FUNC(ir)) {
630 case lwxc1_op: 614 case lwxc1_op:
631 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 615 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
632 xcp->regs[MIPSInst_FT(ir)]); 616 xcp->regs[MIPSInst_FT(ir)]);
633 617
634 fpuemuprivate.stats.loads++; 618 fpuemustats.loads++;
635 if (get_user(val, va)) { 619 if (get_user(val, va)) {
636 fpuemuprivate.stats.errors++; 620 fpuemustats.errors++;
637 return SIGBUS; 621 return SIGBUS;
638 } 622 }
639#ifdef SINGLE_ONLY_FPU
640 if (MIPSInst_FD(ir) & 1) {
641 /* illegal register in single-float
642 * mode
643 */
644 return SIGILL;
645 }
646#endif
647 SITOREG(val, MIPSInst_FD(ir)); 623 SITOREG(val, MIPSInst_FD(ir));
648 break; 624 break;
649 625
650 case swxc1_op: 626 case swxc1_op:
651 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 627 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
652 xcp->regs[MIPSInst_FT(ir)]); 628 xcp->regs[MIPSInst_FT(ir)]);
653 629
654 fpuemuprivate.stats.stores++; 630 fpuemustats.stores++;
655#ifdef SINGLE_ONLY_FPU
656 if (MIPSInst_FS(ir) & 1) {
657 /* illegal register in single-float
658 * mode
659 */
660 return SIGILL;
661 }
662#endif
663 631
664 SIFROMREG(val, MIPSInst_FS(ir)); 632 SIFROMREG(val, MIPSInst_FS(ir));
665 if (put_user(val, va)) { 633 if (put_user(val, va)) {
666 fpuemuprivate.stats.errors++; 634 fpuemustats.errors++;
667 return SIGBUS; 635 return SIGBUS;
668 } 636 }
669 break; 637 break;
@@ -699,8 +667,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
699 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 667 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
700 668
701 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 669 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
702 if (ieee754_csr.nod)
703 ctx->fcr31 |= 0x1000000;
704 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 670 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
705 /*printk ("SIGFPE: fpu csr = %08x\n", 671 /*printk ("SIGFPE: fpu csr = %08x\n",
706 ctx->fcr31); */ 672 ctx->fcr31); */
@@ -715,34 +681,33 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
715 break; 681 break;
716 } 682 }
717 683
718#ifndef SINGLE_ONLY_FPU
719 case d_fmt:{ /* 1 */ 684 case d_fmt:{ /* 1 */
720 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); 685 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
721 ieee754dp fd, fr, fs, ft; 686 ieee754dp fd, fr, fs, ft;
722 u64 *va; 687 u64 __user *va;
723 u64 val; 688 u64 val;
724 689
725 switch (MIPSInst_FUNC(ir)) { 690 switch (MIPSInst_FUNC(ir)) {
726 case ldxc1_op: 691 case ldxc1_op:
727 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 692 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
728 xcp->regs[MIPSInst_FT(ir)]); 693 xcp->regs[MIPSInst_FT(ir)]);
729 694
730 fpuemuprivate.stats.loads++; 695 fpuemustats.loads++;
731 if (get_user(val, va)) { 696 if (get_user(val, va)) {
732 fpuemuprivate.stats.errors++; 697 fpuemustats.errors++;
733 return SIGBUS; 698 return SIGBUS;
734 } 699 }
735 DITOREG(val, MIPSInst_FD(ir)); 700 DITOREG(val, MIPSInst_FD(ir));
736 break; 701 break;
737 702
738 case sdxc1_op: 703 case sdxc1_op:
739 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 704 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
740 xcp->regs[MIPSInst_FT(ir)]); 705 xcp->regs[MIPSInst_FT(ir)]);
741 706
742 fpuemuprivate.stats.stores++; 707 fpuemustats.stores++;
743 DIFROMREG(val, MIPSInst_FS(ir)); 708 DIFROMREG(val, MIPSInst_FS(ir));
744 if (put_user(val, va)) { 709 if (put_user(val, va)) {
745 fpuemuprivate.stats.errors++; 710 fpuemustats.errors++;
746 return SIGBUS; 711 return SIGBUS;
747 } 712 }
748 break; 713 break;
@@ -773,7 +738,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
773 } 738 }
774 break; 739 break;
775 } 740 }
776#endif
777 741
778 case 0x7: /* 7 */ 742 case 0x7: /* 7 */
779 if (MIPSInst_FUNC(ir) != pfetch_op) { 743 if (MIPSInst_FUNC(ir) != pfetch_op) {
@@ -810,7 +774,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
810#endif 774#endif
811 } rv; /* resulting value */ 775 } rv; /* resulting value */
812 776
813 fpuemuprivate.stats.cp1ops++; 777 fpuemustats.cp1ops++;
814 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 778 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
815 case s_fmt:{ /* 0 */ 779 case s_fmt:{ /* 0 */
816 union { 780 union {
@@ -834,7 +798,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
834 goto scopbop; 798 goto scopbop;
835 799
836 /* unary ops */ 800 /* unary ops */
837#if __mips >= 2 || __mips64 801#if __mips >= 2 || defined(__mips64)
838 case fsqrt_op: 802 case fsqrt_op:
839 handler.u = ieee754sp_sqrt; 803 handler.u = ieee754sp_sqrt;
840 goto scopuop; 804 goto scopuop;
@@ -913,9 +877,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
913 case fcvts_op: 877 case fcvts_op:
914 return SIGILL; /* not defined */ 878 return SIGILL; /* not defined */
915 case fcvtd_op:{ 879 case fcvtd_op:{
916#ifdef SINGLE_ONLY_FPU
917 return SIGILL; /* not defined */
918#else
919 ieee754sp fs; 880 ieee754sp fs;
920 881
921 SPFROMREG(fs, MIPSInst_FS(ir)); 882 SPFROMREG(fs, MIPSInst_FS(ir));
@@ -923,7 +884,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
923 rfmt = d_fmt; 884 rfmt = d_fmt;
924 goto copcsr; 885 goto copcsr;
925 } 886 }
926#endif
927 case fcvtw_op:{ 887 case fcvtw_op:{
928 ieee754sp fs; 888 ieee754sp fs;
929 889
@@ -933,7 +893,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
933 goto copcsr; 893 goto copcsr;
934 } 894 }
935 895
936#if __mips >= 2 || __mips64 896#if __mips >= 2 || defined(__mips64)
937 case fround_op: 897 case fround_op:
938 case ftrunc_op: 898 case ftrunc_op:
939 case fceil_op: 899 case fceil_op:
@@ -950,7 +910,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
950 } 910 }
951#endif /* __mips >= 2 */ 911#endif /* __mips >= 2 */
952 912
953#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 913#if defined(__mips64)
954 case fcvtl_op:{ 914 case fcvtl_op:{
955 ieee754sp fs; 915 ieee754sp fs;
956 916
@@ -974,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
974 rfmt = l_fmt; 934 rfmt = l_fmt;
975 goto copcsr; 935 goto copcsr;
976 } 936 }
977#endif /* __mips64 && !fpu(single) */ 937#endif /* defined(__mips64) */
978 938
979 default: 939 default:
980 if (MIPSInst_FUNC(ir) >= fcmp_op) { 940 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1001,7 +961,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1001 break; 961 break;
1002 } 962 }
1003 963
1004#ifndef SINGLE_ONLY_FPU
1005 case d_fmt:{ 964 case d_fmt:{
1006 union { 965 union {
1007 ieee754dp(*b) (ieee754dp, ieee754dp); 966 ieee754dp(*b) (ieee754dp, ieee754dp);
@@ -1024,7 +983,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1024 goto dcopbop; 983 goto dcopbop;
1025 984
1026 /* unary ops */ 985 /* unary ops */
1027#if __mips >= 2 || __mips64 986#if __mips >= 2 || defined(__mips64)
1028 case fsqrt_op: 987 case fsqrt_op:
1029 handler.u = ieee754dp_sqrt; 988 handler.u = ieee754dp_sqrt;
1030 goto dcopuop; 989 goto dcopuop;
@@ -1108,7 +1067,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1108 goto copcsr; 1067 goto copcsr;
1109 } 1068 }
1110 1069
1111#if __mips >= 2 || __mips64 1070#if __mips >= 2 || defined(__mips64)
1112 case fround_op: 1071 case fround_op:
1113 case ftrunc_op: 1072 case ftrunc_op:
1114 case fceil_op: 1073 case fceil_op:
@@ -1125,7 +1084,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1125 } 1084 }
1126#endif 1085#endif
1127 1086
1128#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1087#if defined(__mips64)
1129 case fcvtl_op:{ 1088 case fcvtl_op:{
1130 ieee754dp fs; 1089 ieee754dp fs;
1131 1090
@@ -1149,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1149 rfmt = l_fmt; 1108 rfmt = l_fmt;
1150 goto copcsr; 1109 goto copcsr;
1151 } 1110 }
1152#endif /* __mips >= 3 && !fpu(single) */ 1111#endif /* __mips >= 3 */
1153 1112
1154 default: 1113 default:
1155 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1114 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1177,7 +1136,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1177 } 1136 }
1178 break; 1137 break;
1179 } 1138 }
1180#endif /* ifndef SINGLE_ONLY_FPU */
1181 1139
1182 case w_fmt:{ 1140 case w_fmt:{
1183 ieee754sp fs; 1141 ieee754sp fs;
@@ -1189,21 +1147,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1189 rv.s = ieee754sp_fint(fs.bits); 1147 rv.s = ieee754sp_fint(fs.bits);
1190 rfmt = s_fmt; 1148 rfmt = s_fmt;
1191 goto copcsr; 1149 goto copcsr;
1192#ifndef SINGLE_ONLY_FPU
1193 case fcvtd_op: 1150 case fcvtd_op:
1194 /* convert word to double precision real */ 1151 /* convert word to double precision real */
1195 SPFROMREG(fs, MIPSInst_FS(ir)); 1152 SPFROMREG(fs, MIPSInst_FS(ir));
1196 rv.d = ieee754dp_fint(fs.bits); 1153 rv.d = ieee754dp_fint(fs.bits);
1197 rfmt = d_fmt; 1154 rfmt = d_fmt;
1198 goto copcsr; 1155 goto copcsr;
1199#endif
1200 default: 1156 default:
1201 return SIGILL; 1157 return SIGILL;
1202 } 1158 }
1203 break; 1159 break;
1204 } 1160 }
1205 1161
1206#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1162#if defined(__mips64)
1207 case l_fmt:{ 1163 case l_fmt:{
1208 switch (MIPSInst_FUNC(ir)) { 1164 switch (MIPSInst_FUNC(ir)) {
1209 case fcvts_op: 1165 case fcvts_op:
@@ -1256,18 +1212,16 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1256 ctx->fcr31 &= ~cond; 1212 ctx->fcr31 &= ~cond;
1257 break; 1213 break;
1258 } 1214 }
1259#ifndef SINGLE_ONLY_FPU
1260 case d_fmt: 1215 case d_fmt:
1261 DPTOREG(rv.d, MIPSInst_FD(ir)); 1216 DPTOREG(rv.d, MIPSInst_FD(ir));
1262 break; 1217 break;
1263#endif
1264 case s_fmt: 1218 case s_fmt:
1265 SPTOREG(rv.s, MIPSInst_FD(ir)); 1219 SPTOREG(rv.s, MIPSInst_FD(ir));
1266 break; 1220 break;
1267 case w_fmt: 1221 case w_fmt:
1268 SITOREG(rv.w, MIPSInst_FD(ir)); 1222 SITOREG(rv.w, MIPSInst_FD(ir));
1269 break; 1223 break;
1270#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1224#if defined(__mips64)
1271 case l_fmt: 1225 case l_fmt:
1272 DITOREG(rv.l, MIPSInst_FD(ir)); 1226 DITOREG(rv.l, MIPSInst_FD(ir));
1273 break; 1227 break;
@@ -1279,10 +1233,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1279 return 0; 1233 return 0;
1280} 1234}
1281 1235
1282int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, 1236int fpu_emulator_cop1Handler(struct pt_regs *xcp,
1283 struct mips_fpu_soft_struct *ctx) 1237 struct mips_fpu_soft_struct *ctx)
1284{ 1238{
1285 gpreg_t oldepc, prevepc; 1239 unsigned long oldepc, prevepc;
1286 mips_instruction insn; 1240 mips_instruction insn;
1287 int sig = 0; 1241 int sig = 0;
1288 1242
@@ -1290,19 +1244,24 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
1290 do { 1244 do {
1291 prevepc = xcp->cp0_epc; 1245 prevepc = xcp->cp0_epc;
1292 1246
1293 if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { 1247 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1294 fpuemuprivate.stats.errors++; 1248 fpuemustats.errors++;
1295 return SIGBUS; 1249 return SIGBUS;
1296 } 1250 }
1297 if (insn == 0) 1251 if (insn == 0)
1298 xcp->cp0_epc += 4; /* skip nops */ 1252 xcp->cp0_epc += 4; /* skip nops */
1299 else { 1253 else {
1300 /* Update ieee754_csr. Only relevant if we have a 1254 /*
1301 h/w FPU */ 1255 * The 'ieee754_csr' is an alias of
1302 ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0; 1256 * ctx->fcr31. No need to copy ctx->fcr31 to
1303 ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3]; 1257 * ieee754_csr. But ieee754_csr.rm is ieee
1304 ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f; 1258 * library modes. (not mips rounding mode)
1259 */
1260 /* convert to ieee library modes */
1261 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1305 sig = cop1Emulate(xcp, ctx); 1262 sig = cop1Emulate(xcp, ctx);
1263 /* revert to mips rounding mode */
1264 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1306 } 1265 }
1307 1266
1308 if (cpu_has_fpu) 1267 if (cpu_has_fpu)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-08 18:56:47 -0500