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-rw-r--r--arch/mips/loongson/lemote-2f/Makefile11
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.c130
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.h188
-rw-r--r--arch/mips/loongson/lemote-2f/irq.c134
-rw-r--r--arch/mips/loongson/lemote-2f/pm.c149
-rw-r--r--arch/mips/loongson/lemote-2f/reset.c159
6 files changed, 771 insertions, 0 deletions
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
new file mode 100644
index 000000000000..4d84b27dc41b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for lemote loongson2f family machines
3#
4
5obj-y += irq.o reset.o ec_kb3310b.o
6
7#
8# Suspend Support
9#
10
11obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
new file mode 100644
index 000000000000..4d84111a2cd4
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -0,0 +1,130 @@
1/*
2 * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-04-20
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/spinlock.h>
15#include <linux/delay.h>
16
17#include "ec_kb3310b.h"
18
19static DEFINE_SPINLOCK(index_access_lock);
20static DEFINE_SPINLOCK(port_access_lock);
21
22unsigned char ec_read(unsigned short addr)
23{
24 unsigned char value;
25 unsigned long flags;
26
27 spin_lock_irqsave(&index_access_lock, flags);
28 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
29 outb((addr & 0x00ff), EC_IO_PORT_LOW);
30 value = inb(EC_IO_PORT_DATA);
31 spin_unlock_irqrestore(&index_access_lock, flags);
32
33 return value;
34}
35EXPORT_SYMBOL_GPL(ec_read);
36
37void ec_write(unsigned short addr, unsigned char val)
38{
39 unsigned long flags;
40
41 spin_lock_irqsave(&index_access_lock, flags);
42 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
43 outb((addr & 0x00ff), EC_IO_PORT_LOW);
44 outb(val, EC_IO_PORT_DATA);
45 /* flush the write action */
46 inb(EC_IO_PORT_DATA);
47 spin_unlock_irqrestore(&index_access_lock, flags);
48
49 return;
50}
51EXPORT_SYMBOL_GPL(ec_write);
52
53/*
54 * This function is used for EC command writes and corresponding status queries.
55 */
56int ec_query_seq(unsigned char cmd)
57{
58 int timeout;
59 unsigned char status;
60 unsigned long flags;
61 int ret = 0;
62
63 spin_lock_irqsave(&port_access_lock, flags);
64
65 /* make chip goto reset mode */
66 udelay(EC_REG_DELAY);
67 outb(cmd, EC_CMD_PORT);
68 udelay(EC_REG_DELAY);
69
70 /* check if the command is received by ec */
71 timeout = EC_CMD_TIMEOUT;
72 status = inb(EC_STS_PORT);
73 while (timeout-- && (status & (1 << 1))) {
74 status = inb(EC_STS_PORT);
75 udelay(EC_REG_DELAY);
76 }
77
78 if (timeout <= 0) {
79 printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
80 ret = -EINVAL;
81 } else
82 printk(KERN_INFO
83 "(%x/%d)ec issued command %d status : 0x%x\n",
84 timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
85
86 spin_unlock_irqrestore(&port_access_lock, flags);
87
88 return ret;
89}
90EXPORT_SYMBOL_GPL(ec_query_seq);
91
92/*
93 * Send query command to EC to get the proper event number
94 */
95int ec_query_event_num(void)
96{
97 return ec_query_seq(CMD_GET_EVENT_NUM);
98}
99EXPORT_SYMBOL(ec_query_event_num);
100
101/*
102 * Get event number from EC
103 *
104 * NOTE: This routine must follow the query_event_num function in the
105 * interrupt.
106 */
107int ec_get_event_num(void)
108{
109 int timeout = 100;
110 unsigned char value;
111 unsigned char status;
112
113 udelay(EC_REG_DELAY);
114 status = inb(EC_STS_PORT);
115 udelay(EC_REG_DELAY);
116 while (timeout-- && !(status & (1 << 0))) {
117 status = inb(EC_STS_PORT);
118 udelay(EC_REG_DELAY);
119 }
120 if (timeout <= 0) {
121 pr_info("%s: get event number timeout.\n", __func__);
122
123 return -EINVAL;
124 }
125 value = inb(EC_DAT_PORT);
126 udelay(EC_REG_DELAY);
127
128 return value;
129}
130EXPORT_SYMBOL(ec_get_event_num);
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
new file mode 100644
index 000000000000..1595a21b315b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -0,0 +1,188 @@
1/*
2 * KB3310B Embedded Controller
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-03-14
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _EC_KB3310B_H
14#define _EC_KB3310B_H
15
16extern unsigned char ec_read(unsigned short addr);
17extern void ec_write(unsigned short addr, unsigned char val);
18extern int ec_query_seq(unsigned char cmd);
19extern int ec_query_event_num(void);
20extern int ec_get_event_num(void);
21
22typedef int (*sci_handler) (int status);
23extern sci_handler yeeloong_report_lid_status;
24
25#define SCI_IRQ_NUM 0x0A
26
27/*
28 * The following registers are determined by the EC index configuration.
29 * 1, fill the PORT_HIGH as EC register high part.
30 * 2, fill the PORT_LOW as EC register low part.
31 * 3, fill the PORT_DATA as EC register write data or get the data from it.
32 */
33#define EC_IO_PORT_HIGH 0x0381
34#define EC_IO_PORT_LOW 0x0382
35#define EC_IO_PORT_DATA 0x0383
36
37/*
38 * EC delay time is 500us for register and status access
39 */
40#define EC_REG_DELAY 500 /* unit : us */
41#define EC_CMD_TIMEOUT 0x1000
42
43/*
44 * EC access port for SCI communication
45 */
46#define EC_CMD_PORT 0x66
47#define EC_STS_PORT 0x66
48#define EC_DAT_PORT 0x62
49#define CMD_INIT_IDLE_MODE 0xdd
50#define CMD_EXIT_IDLE_MODE 0xdf
51#define CMD_INIT_RESET_MODE 0xd8
52#define CMD_REBOOT_SYSTEM 0x8c
53#define CMD_GET_EVENT_NUM 0x84
54#define CMD_PROGRAM_PIECE 0xda
55
56/* temperature & fan registers */
57#define REG_TEMPERATURE_VALUE 0xF458
58#define REG_FAN_AUTO_MAN_SWITCH 0xF459
59#define BIT_FAN_AUTO 0
60#define BIT_FAN_MANUAL 1
61#define REG_FAN_CONTROL 0xF4D2
62#define BIT_FAN_CONTROL_ON (1 << 0)
63#define BIT_FAN_CONTROL_OFF (0 << 0)
64#define REG_FAN_STATUS 0xF4DA
65#define BIT_FAN_STATUS_ON (1 << 0)
66#define BIT_FAN_STATUS_OFF (0 << 0)
67#define REG_FAN_SPEED_HIGH 0xFE22
68#define REG_FAN_SPEED_LOW 0xFE23
69#define REG_FAN_SPEED_LEVEL 0xF4CC
70/* fan speed divider */
71#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
72
73/* battery registers */
74#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
75#define REG_BAT_DESIGN_CAP_LOW 0xF77E
76#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
77#define REG_BAT_FULLCHG_CAP_LOW 0xF781
78#define REG_BAT_DESIGN_VOL_HIGH 0xF782
79#define REG_BAT_DESIGN_VOL_LOW 0xF783
80#define REG_BAT_CURRENT_HIGH 0xF784
81#define REG_BAT_CURRENT_LOW 0xF785
82#define REG_BAT_VOLTAGE_HIGH 0xF786
83#define REG_BAT_VOLTAGE_LOW 0xF787
84#define REG_BAT_TEMPERATURE_HIGH 0xF788
85#define REG_BAT_TEMPERATURE_LOW 0xF789
86#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
87#define REG_BAT_RELATIVE_CAP_LOW 0xF493
88#define REG_BAT_VENDOR 0xF4C4
89#define FLAG_BAT_VENDOR_SANYO 0x01
90#define FLAG_BAT_VENDOR_SIMPLO 0x02
91#define REG_BAT_CELL_COUNT 0xF4C6
92#define FLAG_BAT_CELL_3S1P 0x03
93#define FLAG_BAT_CELL_3S2P 0x06
94#define REG_BAT_CHARGE 0xF4A2
95#define FLAG_BAT_CHARGE_DISCHARGE 0x01
96#define FLAG_BAT_CHARGE_CHARGE 0x02
97#define FLAG_BAT_CHARGE_ACPOWER 0x00
98#define REG_BAT_STATUS 0xF4B0
99#define BIT_BAT_STATUS_LOW (1 << 5)
100#define BIT_BAT_STATUS_DESTROY (1 << 2)
101#define BIT_BAT_STATUS_FULL (1 << 1)
102#define BIT_BAT_STATUS_IN (1 << 0)
103#define REG_BAT_CHARGE_STATUS 0xF4B1
104#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
105#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
106#define REG_BAT_STATE 0xF482
107#define BIT_BAT_STATE_CHARGING (1 << 1)
108#define BIT_BAT_STATE_DISCHARGING (1 << 0)
109#define REG_BAT_POWER 0xF440
110#define BIT_BAT_POWER_S3 (1 << 2)
111#define BIT_BAT_POWER_ON (1 << 1)
112#define BIT_BAT_POWER_ACIN (1 << 0)
113
114/* other registers */
115/* Audio: rd/wr */
116#define REG_AUDIO_VOLUME 0xF46C
117#define REG_AUDIO_MUTE 0xF4E7
118#define REG_AUDIO_BEEP 0xF4D0
119/* USB port power or not: rd/wr */
120#define REG_USB0_FLAG 0xF461
121#define REG_USB1_FLAG 0xF462
122#define REG_USB2_FLAG 0xF463
123#define BIT_USB_FLAG_ON 1
124#define BIT_USB_FLAG_OFF 0
125/* LID */
126#define REG_LID_DETECT 0xF4BD
127#define BIT_LID_DETECT_ON 1
128#define BIT_LID_DETECT_OFF 0
129/* CRT */
130#define REG_CRT_DETECT 0xF4AD
131#define BIT_CRT_DETECT_PLUG 1
132#define BIT_CRT_DETECT_UNPLUG 0
133/* LCD backlight brightness adjust: 9 levels */
134#define REG_DISPLAY_BRIGHTNESS 0xF4F5
135/* Black screen Status */
136#define BIT_DISPLAY_LCD_ON 1
137#define BIT_DISPLAY_LCD_OFF 0
138/* LCD backlight control: off/restore */
139#define REG_BACKLIGHT_CTRL 0xF7BD
140#define BIT_BACKLIGHT_ON 1
141#define BIT_BACKLIGHT_OFF 0
142/* Reset the machine auto-clear: rd/wr */
143#define REG_RESET 0xF4EC
144#define BIT_RESET_ON 1
145/* Light the led: rd/wr */
146#define REG_LED 0xF4C8
147#define BIT_LED_RED_POWER (1 << 0)
148#define BIT_LED_ORANGE_POWER (1 << 1)
149#define BIT_LED_GREEN_CHARGE (1 << 2)
150#define BIT_LED_RED_CHARGE (1 << 3)
151#define BIT_LED_NUMLOCK (1 << 4)
152/* Test led mode, all led on/off */
153#define REG_LED_TEST 0xF4C2
154#define BIT_LED_TEST_IN 1
155#define BIT_LED_TEST_OUT 0
156/* Camera on/off */
157#define REG_CAMERA_STATUS 0xF46A
158#define BIT_CAMERA_STATUS_ON 1
159#define BIT_CAMERA_STATUS_OFF 0
160#define REG_CAMERA_CONTROL 0xF7B7
161#define BIT_CAMERA_CONTROL_OFF 0
162#define BIT_CAMERA_CONTROL_ON 1
163/* Wlan Status */
164#define REG_WLAN 0xF4FA
165#define BIT_WLAN_ON 1
166#define BIT_WLAN_OFF 0
167#define REG_DISPLAY_LCD 0xF79F
168
169/* SCI Event Number from EC */
170enum {
171 EVENT_LID = 0x23, /* LID open/close */
172 EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */
173 EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
174 EVENT_OVERTEMP, /* Over-temperature happened */
175 EVENT_CRT_DETECT, /* CRT is connected */
176 EVENT_CAMERA, /* Camera on/off */
177 EVENT_USB_OC2, /* USB2 Over Current occurred */
178 EVENT_USB_OC0, /* USB0 Over Current occurred */
179 EVENT_BLACK_SCREEN, /* Turn on/off backlight */
180 EVENT_AUDIO_MUTE, /* Mute on/off */
181 EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
182 EVENT_AC_BAT, /* AC & Battery relative issue */
183 EVENT_AUDIO_VOLUME, /* Volume adjust */
184 EVENT_WLAN, /* Wlan on/off */
185 EVENT_END
186};
187
188#endif /* !_EC_KB3310B_H */
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
new file mode 100644
index 000000000000..77d32f9cf31e
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2007 Lemote Inc.
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/interrupt.h>
12#include <linux/module.h>
13
14#include <asm/irq_cpu.h>
15#include <asm/i8259.h>
16#include <asm/mipsregs.h>
17
18#include <loongson.h>
19#include <machine.h>
20
21#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
23#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
24#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
25#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
26
27#define LOONGSON_INT_BIT_INT0 (1 << 11)
28#define LOONGSON_INT_BIT_INT1 (1 << 12)
29
30/*
31 * The generic i8259_irq() make the kernel hang on booting. Since we cannot
32 * get the irq via the IRR directly, we access the ISR instead.
33 */
34int mach_i8259_irq(void)
35{
36 int irq, isr;
37
38 irq = -1;
39
40 if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
41 spin_lock(&i8259A_lock);
42 isr = inb(PIC_MASTER_CMD) &
43 ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
44 if (!isr)
45 isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
46 irq = ffs(isr) - 1;
47 if (unlikely(irq == 7)) {
48 /*
49 * This may be a spurious interrupt.
50 *
51 * Read the interrupt status register (ISR). If the most
52 * significant bit is not set then there is no valid
53 * interrupt.
54 */
55 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
56 if (~inb(PIC_MASTER_ISR) & 0x80)
57 irq = -1;
58 }
59 spin_unlock(&i8259A_lock);
60 }
61
62 return irq;
63}
64EXPORT_SYMBOL(mach_i8259_irq);
65
66static void i8259_irqdispatch(void)
67{
68 int irq;
69
70 irq = mach_i8259_irq();
71 if (irq >= 0)
72 do_IRQ(irq);
73 else
74 spurious_interrupt();
75}
76
77void mach_irq_dispatch(unsigned int pending)
78{
79 if (pending & CAUSEF_IP7)
80 do_IRQ(LOONGSON_TIMER_IRQ);
81 else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
82#ifdef CONFIG_OPROFILE
83 do_IRQ(LOONGSON2_PERFCNT_IRQ);
84#endif
85 bonito_irqdispatch();
86 } else if (pending & CAUSEF_IP3) /* CPU UART */
87 do_IRQ(LOONGSON_UART_IRQ);
88 else if (pending & CAUSEF_IP2) /* South Bridge */
89 i8259_irqdispatch();
90 else
91 spurious_interrupt();
92}
93
94void __init set_irq_trigger_mode(void)
95{
96 /* setup cs5536 as high level trigger */
97 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99}
100
101static irqreturn_t ip6_action(int cpl, void *dev_id)
102{
103 return IRQ_HANDLED;
104}
105
106struct irqaction ip6_irqaction = {
107 .handler = ip6_action,
108 .name = "cascade",
109 .flags = IRQF_SHARED,
110};
111
112struct irqaction cascade_irqaction = {
113 .handler = no_action,
114 .name = "cascade",
115};
116
117void __init mach_init_irq(void)
118{
119 /* init all controller
120 * 0-15 ------> i8259 interrupt
121 * 16-23 ------> mips cpu interrupt
122 * 32-63 ------> bonito irq
123 */
124
125 /* Sets the first-level interrupt dispatcher. */
126 mips_cpu_irq_init();
127 init_i8259_irqs();
128 bonito_irq_init();
129
130 /* setup north bridge irq (bonito) */
131 setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
132 /* setup source bridge irq (i8259) */
133 setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
134}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
new file mode 100644
index 000000000000..d7af2e616592
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -0,0 +1,149 @@
1/*
2 * Lemote loongson2f family machines' specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/suspend.h>
14#include <linux/interrupt.h>
15#include <linux/pm.h>
16#include <linux/i8042.h>
17#include <linux/module.h>
18
19#include <asm/i8259.h>
20#include <asm/mipsregs.h>
21#include <asm/bootinfo.h>
22
23#include <loongson.h>
24
25#include <cs5536/cs5536_mfgpt.h>
26#include "ec_kb3310b.h"
27
28#define I8042_KBD_IRQ 1
29#define I8042_CTR_KBDINT 0x01
30#define I8042_CTR_KBDDIS 0x10
31
32static unsigned char i8042_ctr;
33
34static int i8042_enable_kbd_port(void)
35{
36 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
37 pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
38 "\n");
39 return -EIO;
40 }
41
42 i8042_ctr &= ~I8042_CTR_KBDDIS;
43 i8042_ctr |= I8042_CTR_KBDINT;
44
45 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
46 i8042_ctr &= ~I8042_CTR_KBDINT;
47 i8042_ctr |= I8042_CTR_KBDDIS;
48 pr_err("i8042.c: Failed to enable KBD port.\n");
49
50 return -EIO;
51 }
52
53 return 0;
54}
55
56void setup_wakeup_events(void)
57{
58 int irq_mask;
59
60 switch (mips_machtype) {
61 case MACH_LEMOTE_ML2F7:
62 case MACH_LEMOTE_YL2F89:
63 /* open the keyboard irq in i8259A */
64 outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
65 irq_mask = inb(PIC_MASTER_IMR);
66
67 /* enable keyboard port */
68 i8042_enable_kbd_port();
69
70 /* Wakeup CPU via SCI lid open event */
71 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
72 inb(PIC_MASTER_IMR);
73 outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
74 inb(PIC_SLAVE_IMR);
75
76 break;
77
78 default:
79 break;
80 }
81}
82
83static struct delayed_work lid_task;
84static int initialized;
85/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
86sci_handler yeeloong_report_lid_status;
87EXPORT_SYMBOL(yeeloong_report_lid_status);
88static void yeeloong_lid_update_task(struct work_struct *work)
89{
90 if (yeeloong_report_lid_status)
91 yeeloong_report_lid_status(BIT_LID_DETECT_ON);
92}
93
94int wakeup_loongson(void)
95{
96 int irq;
97
98 /* query the interrupt number */
99 irq = mach_i8259_irq();
100 if (irq < 0)
101 return 0;
102
103 printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
104
105 if (irq == I8042_KBD_IRQ)
106 return 1;
107 else if (irq == SCI_IRQ_NUM) {
108 int ret, sci_event;
109 /* query the event number */
110 ret = ec_query_seq(CMD_GET_EVENT_NUM);
111 if (ret < 0)
112 return 0;
113 sci_event = ec_get_event_num();
114 if (sci_event < 0)
115 return 0;
116 if (sci_event == EVENT_LID) {
117 int lid_status;
118 /* check the LID status */
119 lid_status = ec_read(REG_LID_DETECT);
120 /* wakeup cpu when people open the LID */
121 if (lid_status == BIT_LID_DETECT_ON) {
122 /* If we call it directly here, the WARNING
123 * will be sent out by getnstimeofday
124 * via "WARN_ON(timekeeping_suspended);"
125 * because we can not schedule in suspend mode.
126 */
127 if (initialized == 0) {
128 INIT_DELAYED_WORK(&lid_task,
129 yeeloong_lid_update_task);
130 initialized = 1;
131 }
132 schedule_delayed_work(&lid_task, 1);
133 return 1;
134 }
135 }
136 }
137
138 return 0;
139}
140
141void __weak mach_suspend(void)
142{
143 disable_mfgpt0_counter();
144}
145
146void __weak mach_resume(void)
147{
148 enable_mfgpt0_counter();
149}
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
new file mode 100644
index 000000000000..51d1a60d5349
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -0,0 +1,159 @@
1/* Board-specific reboot/shutdown routines
2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 *
5 * Copyright (C) 2009 Lemote Inc.
6 * Author: Wu Zhangjin, wuzj@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/types.h>
17
18#include <asm/bootinfo.h>
19
20#include <loongson.h>
21
22#include <cs5536/cs5536.h>
23#include "ec_kb3310b.h"
24
25static void reset_cpu(void)
26{
27 /*
28 * reset cpu to full speed, this is needed when enabling cpu frequency
29 * scalling
30 */
31 LOONGSON_CHIPCFG0 |= 0x7;
32}
33
34/* reset support for fuloong2f */
35
36static void fl2f_reboot(void)
37{
38 reset_cpu();
39
40 /* send a reset signal to south bridge.
41 *
42 * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
43 * normally with this reset operation and it will not work in PMON, but
44 * you can type halt command and then reboot, seems the hardware reset
45 * logic not work normally.
46 */
47 {
48 u32 hi, lo;
49 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
50 lo |= 0x00000001;
51 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
52 }
53}
54
55static void fl2f_shutdown(void)
56{
57 u32 hi, lo, val;
58 int gpio_base;
59
60 /* get gpio base */
61 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
62 gpio_base = lo & 0xff00;
63
64 /* make cs5536 gpio13 output enable */
65 val = inl(gpio_base + GPIOL_OUT_EN);
66 val &= ~(1 << (16 + 13));
67 val |= (1 << 13);
68 outl(val, gpio_base + GPIOL_OUT_EN);
69 mmiowb();
70 /* make cs5536 gpio13 output low level voltage. */
71 val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
72 val |= (1 << (16 + 13));
73 outl(val, gpio_base + GPIOL_OUT_VAL);
74 mmiowb();
75}
76
77/* reset support for yeeloong2f and mengloong2f notebook */
78
79void ml2f_reboot(void)
80{
81 reset_cpu();
82
83 /* sending an reset signal to EC(embedded controller) */
84 ec_write(REG_RESET, BIT_RESET_ON);
85}
86
87#define yl2f89_reboot ml2f_reboot
88
89/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
90#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
91#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e
92#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
93#define REG_SHUTDOWN_HIGH 0xFC
94#define REG_SHUTDOWN_LOW 0x29
95#define BIT_SHUTDOWN_ON (1 << 1)
96
97static void ml2f_shutdown(void)
98{
99 u8 val;
100 u64 i;
101
102 outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
103 outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
104 mmiowb();
105 val = inb(EC_SHUTDOWN_IO_PORT_DATA);
106 outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
107 mmiowb();
108 /* need enough wait here... how many microseconds needs? */
109 for (i = 0; i < 0x10000; i++)
110 delay();
111 outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
112 mmiowb();
113}
114
115static void yl2f89_shutdown(void)
116{
117 /* cpu-gpio0 output low */
118 LOONGSON_GPIODATA &= ~0x00000001;
119 /* cpu-gpio0 as output */
120 LOONGSON_GPIOIE &= ~0x00000001;
121}
122
123void mach_prepare_reboot(void)
124{
125 switch (mips_machtype) {
126 case MACH_LEMOTE_FL2F:
127 case MACH_LEMOTE_NAS:
128 case MACH_LEMOTE_LL2F:
129 fl2f_reboot();
130 break;
131 case MACH_LEMOTE_ML2F7:
132 ml2f_reboot();
133 break;
134 case MACH_LEMOTE_YL2F89:
135 yl2f89_reboot();
136 break;
137 default:
138 break;
139 }
140}
141
142void mach_prepare_shutdown(void)
143{
144 switch (mips_machtype) {
145 case MACH_LEMOTE_FL2F:
146 case MACH_LEMOTE_NAS:
147 case MACH_LEMOTE_LL2F:
148 fl2f_shutdown();
149 break;
150 case MACH_LEMOTE_ML2F7:
151 ml2f_shutdown();
152 break;
153 case MACH_LEMOTE_YL2F89:
154 yl2f89_shutdown();
155 break;
156 default:
157 break;
158 }
159}
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