2 files changed, 5 insertions, 10 deletions

diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile
index 3aba5fcc09dc..b7622720c1ad 100644
--- a/arch/mips/loongson/fuloong-2e/Makefile
+++ b/arch/mips/loongson/fuloong-2e/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y += irq.o reset.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..d61a04222b87 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -30,7 +30,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
         if (pending & CAUSEF_IP7)
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP6) /* perf counter loverflow */
-                do_IRQ(LOONGSON2_PERFCNT_IRQ);
+                do_perfcnt_IRQ();
         else if (pending & CAUSEF_IP5)
                 i8259_irqdispatch();
         else if (pending & CAUSEF_IP2)
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
         .name = "cascade",
 };
 
-void __init set_irq_trigger_mode(void)
-{
-        /* most bonito irq should be level triggered */
-        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
-            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
 void __init mach_init_irq(void)
 {
         /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
          *   32-63        ------> bonito irq
          */
 
+        /* most bonito irq should be level triggered */
+        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
+
         /* Sets the first-level interrupt dispatcher. */
         mips_cpu_irq_init();
         init_i8259_irqs();