1 files changed, 6 insertions, 46 deletions

diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 9585f5aa7cce..7888cf69424a 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -7,39 +7,12 @@
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
  */
-#include <linux/delay.h>
 #include <linux/interrupt.h>
 
 #include <asm/irq_cpu.h>
 #include <asm/i8259.h>
 
 #include <loongson.h>
-/*
- * the first level int-handler will jump here if it is a bonito irq
- */
-static void bonito_irqdispatch(void)
-{
-        u32 int_status;
-        int i;
-
-        /* workaround the IO dma problem: let cpu looping to allow DMA finish */
-        int_status = BONITO_INTISR;
-        if (int_status & (1 << 10)) {
-                while (int_status & (1 << 10)) {
-                        udelay(1);
-                        int_status = BONITO_INTISR;
-                }
-        }
-
-        /* Get pending sources, masked by current enables */
-        int_status = BONITO_INTISR & BONITO_INTEN;
-
-        if (int_status != 0) {
-                i = __ffs(int_status);
-                int_status &= ~(1 << i);
-                do_IRQ(BONITO_IRQ_BASE + i);
-        }
-}
 
 static void i8259_irqdispatch(void)
 {
@@ -52,10 +25,8 @@ static void i8259_irqdispatch(void)
                 spurious_interrupt();
 }
 
-asmlinkage void plat_irq_dispatch(void)
+asmlinkage void mach_irq_dispatch(unsigned int pending)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
         if (pending & CAUSEF_IP7)
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP6) /* perf counter loverflow */
@@ -73,26 +44,15 @@ static struct irqaction cascade_irqaction = {
         .name = "cascade",
 };
 
-void __init arch_init_irq(void)
+void __init set_irq_trigger_mode(void)
 {
-        /*
-         * Clear all of the interrupts while we change the able around a bit.
-         * int-handler is not on bootstrap
-         */
-        clear_c0_status(ST0_IM | ST0_BEV);
-        local_irq_disable();
-
         /* most bonito irq should be level triggered */
         BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
-                BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
-        BONITO_INTSTEER = 0;
-
-        /*
-         * Mask out all interrupt by writing "1" to all bit position in
-         * the interrupt reset reg.
-         */
-        BONITO_INTENCLR = ~0;
+            BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
+}
 
+void __init mach_init_irq(void)
+{
         /* init all controller
          *   0-15         ------> i8259 interrupt
          *   16-23        ------> mips cpu interrupt