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-rw-r--r--arch/mips/lib/iomap.c18
-rw-r--r--arch/mips/lib/memset.S6
-rw-r--r--arch/mips/lib/mips-atomic.c20
-rw-r--r--arch/mips/lib/r3k_dump_tlb.c11
-rw-r--r--arch/mips/lib/strlen_user.S3
5 files changed, 17 insertions, 41 deletions
diff --git a/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c
index e3acb2dad33a..8e7e378ce51c 100644
--- a/arch/mips/lib/iomap.c
+++ b/arch/mips/lib/iomap.c
@@ -97,14 +97,14 @@ EXPORT_SYMBOL(iowrite32be);
97 97
98/* 98/*
99 * These are the "repeat MMIO read/write" functions. 99 * These are the "repeat MMIO read/write" functions.
100 * Note the "__raw" accesses, since we don't want to 100 * Note the "__mem" accesses, since we want to convert
101 * convert to CPU byte order. We write in "IO byte 101 * to CPU byte order if the host bus happens to not match the
102 * order" (we also don't have IO barriers). 102 * endianness of PCI/ISA (see mach-generic/mangle-port.h).
103 */ 103 */
104static inline void mmio_insb(void __iomem *addr, u8 *dst, int count) 104static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
105{ 105{
106 while (--count >= 0) { 106 while (--count >= 0) {
107 u8 data = __raw_readb(addr); 107 u8 data = __mem_readb(addr);
108 *dst = data; 108 *dst = data;
109 dst++; 109 dst++;
110 } 110 }
@@ -113,7 +113,7 @@ static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
113static inline void mmio_insw(void __iomem *addr, u16 *dst, int count) 113static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
114{ 114{
115 while (--count >= 0) { 115 while (--count >= 0) {
116 u16 data = __raw_readw(addr); 116 u16 data = __mem_readw(addr);
117 *dst = data; 117 *dst = data;
118 dst++; 118 dst++;
119 } 119 }
@@ -122,7 +122,7 @@ static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
122static inline void mmio_insl(void __iomem *addr, u32 *dst, int count) 122static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
123{ 123{
124 while (--count >= 0) { 124 while (--count >= 0) {
125 u32 data = __raw_readl(addr); 125 u32 data = __mem_readl(addr);
126 *dst = data; 126 *dst = data;
127 dst++; 127 dst++;
128 } 128 }
@@ -131,7 +131,7 @@ static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
131static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count) 131static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
132{ 132{
133 while (--count >= 0) { 133 while (--count >= 0) {
134 __raw_writeb(*src, addr); 134 __mem_writeb(*src, addr);
135 src++; 135 src++;
136 } 136 }
137} 137}
@@ -139,7 +139,7 @@ static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
139static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count) 139static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
140{ 140{
141 while (--count >= 0) { 141 while (--count >= 0) {
142 __raw_writew(*src, addr); 142 __mem_writew(*src, addr);
143 src++; 143 src++;
144 } 144 }
145} 145}
@@ -147,7 +147,7 @@ static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
147static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count) 147static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
148{ 148{
149 while (--count >= 0) { 149 while (--count >= 0) {
150 __raw_writel(*src, addr); 150 __mem_writel(*src, addr);
151 src++; 151 src++;
152 } 152 }
153} 153}
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 7b0e5462ca51..c8fe6b1968fb 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -114,8 +114,7 @@
114 R10KCBARRIER(0(ra)) 114 R10KCBARRIER(0(ra))
115#ifdef __MIPSEB__ 115#ifdef __MIPSEB__
116 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */ 116 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
117#endif 117#else
118#ifdef __MIPSEL__
119 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */ 118 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
120#endif 119#endif
121 PTR_SUBU a0, t0 /* long align ptr */ 120 PTR_SUBU a0, t0 /* long align ptr */
@@ -164,8 +163,7 @@
164 R10KCBARRIER(0(ra)) 163 R10KCBARRIER(0(ra))
165#ifdef __MIPSEB__ 164#ifdef __MIPSEB__
166 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@) 165 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
167#endif 166#else
168#ifdef __MIPSEL__
169 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@) 167 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
170#endif 168#endif
1711: jr ra 1691: jr ra
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
index 57bcdaf1f1c8..be777d9a3f85 100644
--- a/arch/mips/lib/mips-atomic.c
+++ b/arch/mips/lib/mips-atomic.c
@@ -42,15 +42,11 @@ notrace void arch_local_irq_disable(void)
42 __asm__ __volatile__( 42 __asm__ __volatile__(
43 " .set push \n" 43 " .set push \n"
44 " .set noat \n" 44 " .set noat \n"
45#if defined(CONFIG_CPU_MIPSR2)
46 /* see irqflags.h for inline function */
47#else
48 " mfc0 $1,$12 \n" 45 " mfc0 $1,$12 \n"
49 " ori $1,0x1f \n" 46 " ori $1,0x1f \n"
50 " xori $1,0x1f \n" 47 " xori $1,0x1f \n"
51 " .set noreorder \n" 48 " .set noreorder \n"
52 " mtc0 $1,$12 \n" 49 " mtc0 $1,$12 \n"
53#endif
54 " " __stringify(__irq_disable_hazard) " \n" 50 " " __stringify(__irq_disable_hazard) " \n"
55 " .set pop \n" 51 " .set pop \n"
56 : /* no outputs */ 52 : /* no outputs */
@@ -72,15 +68,11 @@ notrace unsigned long arch_local_irq_save(void)
72 " .set push \n" 68 " .set push \n"
73 " .set reorder \n" 69 " .set reorder \n"
74 " .set noat \n" 70 " .set noat \n"
75#if defined(CONFIG_CPU_MIPSR2)
76 /* see irqflags.h for inline function */
77#else
78 " mfc0 %[flags], $12 \n" 71 " mfc0 %[flags], $12 \n"
79 " ori $1, %[flags], 0x1f \n" 72 " ori $1, %[flags], 0x1f \n"
80 " xori $1, 0x1f \n" 73 " xori $1, 0x1f \n"
81 " .set noreorder \n" 74 " .set noreorder \n"
82 " mtc0 $1, $12 \n" 75 " mtc0 $1, $12 \n"
83#endif
84 " " __stringify(__irq_disable_hazard) " \n" 76 " " __stringify(__irq_disable_hazard) " \n"
85 " .set pop \n" 77 " .set pop \n"
86 : [flags] "=r" (flags) 78 : [flags] "=r" (flags)
@@ -103,18 +95,12 @@ notrace void arch_local_irq_restore(unsigned long flags)
103 " .set push \n" 95 " .set push \n"
104 " .set noreorder \n" 96 " .set noreorder \n"
105 " .set noat \n" 97 " .set noat \n"
106#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
107 /* see irqflags.h for inline function */
108#elif defined(CONFIG_CPU_MIPSR2)
109 /* see irqflags.h for inline function */
110#else
111 " mfc0 $1, $12 \n" 98 " mfc0 $1, $12 \n"
112 " andi %[flags], 1 \n" 99 " andi %[flags], 1 \n"
113 " ori $1, 0x1f \n" 100 " ori $1, 0x1f \n"
114 " xori $1, 0x1f \n" 101 " xori $1, 0x1f \n"
115 " or %[flags], $1 \n" 102 " or %[flags], $1 \n"
116 " mtc0 %[flags], $12 \n" 103 " mtc0 %[flags], $12 \n"
117#endif
118 " " __stringify(__irq_disable_hazard) " \n" 104 " " __stringify(__irq_disable_hazard) " \n"
119 " .set pop \n" 105 " .set pop \n"
120 : [flags] "=r" (__tmp1) 106 : [flags] "=r" (__tmp1)
@@ -136,18 +122,12 @@ notrace void __arch_local_irq_restore(unsigned long flags)
136 " .set push \n" 122 " .set push \n"
137 " .set noreorder \n" 123 " .set noreorder \n"
138 " .set noat \n" 124 " .set noat \n"
139#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
140 /* see irqflags.h for inline function */
141#elif defined(CONFIG_CPU_MIPSR2)
142 /* see irqflags.h for inline function */
143#else
144 " mfc0 $1, $12 \n" 125 " mfc0 $1, $12 \n"
145 " andi %[flags], 1 \n" 126 " andi %[flags], 1 \n"
146 " ori $1, 0x1f \n" 127 " ori $1, 0x1f \n"
147 " xori $1, 0x1f \n" 128 " xori $1, 0x1f \n"
148 " or %[flags], $1 \n" 129 " or %[flags], $1 \n"
149 " mtc0 %[flags], $12 \n" 130 " mtc0 %[flags], $12 \n"
150#endif
151 " " __stringify(__irq_disable_hazard) " \n" 131 " " __stringify(__irq_disable_hazard) " \n"
152 " .set pop \n" 132 " .set pop \n"
153 : [flags] "=r" (__tmp1) 133 : [flags] "=r" (__tmp1)
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 1ef365ab3cd3..975a13855116 100644
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -9,6 +9,7 @@
9#include <linux/mm.h> 9#include <linux/mm.h>
10 10
11#include <asm/mipsregs.h> 11#include <asm/mipsregs.h>
12#include <asm/mmu_context.h>
12#include <asm/page.h> 13#include <asm/page.h>
13#include <asm/pgtable.h> 14#include <asm/pgtable.h>
14#include <asm/tlbdebug.h> 15#include <asm/tlbdebug.h>
@@ -21,7 +22,7 @@ static void dump_tlb(int first, int last)
21 unsigned int asid; 22 unsigned int asid;
22 unsigned long entryhi, entrylo0; 23 unsigned long entryhi, entrylo0;
23 24
24 asid = read_c0_entryhi() & 0xfc0; 25 asid = read_c0_entryhi() & ASID_MASK;
25 26
26 for (i = first; i <= last; i++) { 27 for (i = first; i <= last; i++) {
27 write_c0_index(i<<8); 28 write_c0_index(i<<8);
@@ -34,8 +35,8 @@ static void dump_tlb(int first, int last)
34 entrylo0 = read_c0_entrylo0(); 35 entrylo0 = read_c0_entrylo0();
35 36
36 /* Unused entries have a virtual address of KSEG0. */ 37 /* Unused entries have a virtual address of KSEG0. */
37 if ((entryhi & 0xfffff000) != 0x80000000 38 if ((entryhi & PAGE_MASK) != KSEG0
38 && (entryhi & 0xfc0) == asid) { 39 && (entryhi & ASID_MASK) == asid) {
39 /* 40 /*
40 * Only print entries in use 41 * Only print entries in use
41 */ 42 */
@@ -43,8 +44,8 @@ static void dump_tlb(int first, int last)
43 44
44 printk("va=%08lx asid=%08lx" 45 printk("va=%08lx asid=%08lx"
45 " [pa=%06lx n=%d d=%d v=%d g=%d]", 46 " [pa=%06lx n=%d d=%d v=%d g=%d]",
46 (entryhi & 0xfffff000), 47 entryhi & PAGE_MASK,
47 entryhi & 0xfc0, 48 entryhi & ASID_MASK,
48 entrylo0 & PAGE_MASK, 49 entrylo0 & PAGE_MASK,
49 (entrylo0 & (1 << 11)) ? 1 : 0, 50 (entrylo0 & (1 << 11)) ? 1 : 0,
50 (entrylo0 & (1 << 10)) ? 1 : 0, 51 (entrylo0 & (1 << 10)) ? 1 : 0,
diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S
index bef65c98df59..929bbacd697e 100644
--- a/arch/mips/lib/strlen_user.S
+++ b/arch/mips/lib/strlen_user.S
@@ -28,7 +28,6 @@ LEAF(__strlen_\func\()_asm)
28 and v0, a0 28 and v0, a0
29 bnez v0, .Lfault\@ 29 bnez v0, .Lfault\@
30 30
31FEXPORT(__strlen_\func\()_nocheck_asm)
32 move v0, a0 31 move v0, a0
33.ifeqs "\func", "kernel" 32.ifeqs "\func", "kernel"
341: EX(lbu, v1, (v0), .Lfault\@) 331: EX(lbu, v1, (v0), .Lfault\@)
@@ -48,9 +47,7 @@ FEXPORT(__strlen_\func\()_nocheck_asm)
48#ifndef CONFIG_EVA 47#ifndef CONFIG_EVA
49 /* Set aliases */ 48 /* Set aliases */
50 .global __strlen_user_asm 49 .global __strlen_user_asm
51 .global __strlen_user_nocheck_asm
52 .set __strlen_user_asm, __strlen_kernel_asm 50 .set __strlen_user_asm, __strlen_kernel_asm
53 .set __strlen_user_nocheck_asm, __strlen_kernel_nocheck_asm
54#endif 51#endif
55 52
56__BUILD_STRLEN_ASM kernel 53__BUILD_STRLEN_ASM kernel
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 18:40:44 -0400