1 files changed, 0 insertions, 143 deletions
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c
deleted file mode 100644
index 1d0a09f3b832..000000000000
--- a/arch/mips/lemote/lm2e/irq.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
- * Author: Fuxin Zhang, zhangfx@lemote.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-#include <asm/mips-boards/bonito64.h>
-/*
- * the first level int-handler will jump here if it is a bonito irq
- */
-static void bonito_irqdispatch(void)
-{
-        u32 int_status;
-        int i;
-        /* workaround the IO dma problem: let cpu looping to allow DMA finish */
-        int_status = BONITO_INTISR;
-        if (int_status & (1 << 10)) {
-                while (int_status & (1 << 10)) {
-                        udelay(1);
-                        int_status = BONITO_INTISR;
-                }
-        }
-        /* Get pending sources, masked by current enables */
-        int_status = BONITO_INTISR & BONITO_INTEN;
-        if (int_status != 0) {
-                i = __ffs(int_status);
-                int_status &= ~(1 << i);
-                do_IRQ(BONITO_IRQ_BASE + i);
-        }
-}
-static void i8259_irqdispatch(void)
-{
-        int irq;
-        irq = i8259_irq();
-        if (irq >= 0) {
-                do_IRQ(irq);
-        } else {
-                spurious_interrupt();
-        }
-}
-asmlinkage void plat_irq_dispatch(void)
-{
-        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
-        if (pending & CAUSEF_IP7) {
-                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
-        } else if (pending & CAUSEF_IP5) {
-                i8259_irqdispatch();
-        } else if (pending & CAUSEF_IP2) {
-                bonito_irqdispatch();
-        } else {
-                spurious_interrupt();
-        }
-}
-static struct irqaction cascade_irqaction = {
-        .handler = no_action,
-        .name = "cascade",
-};
-void __init arch_init_irq(void)
-{
-        extern void bonito_irq_init(void);
-        /*
-         * Clear all of the interrupts while we change the able around a bit.
-         * int-handler is not on bootstrap
-         */
-        clear_c0_status(ST0_IM | ST0_BEV);
-        local_irq_disable();
-        /* most bonito irq should be level triggered */
-        BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
-                BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
-        BONITO_INTSTEER = 0;
-        /*
-         * Mask out all interrupt by writing "1" to all bit position in
-         * the interrupt reset reg.
-         */
-        BONITO_INTENCLR = ~0;
-        /* init all controller
-         *   0-15         ------> i8259 interrupt
-         *   16-23        ------> mips cpu interrupt
-         *   32-63        ------> bonito irq
-         */
-        /* Sets the first-level interrupt dispatcher. */
-        mips_cpu_irq_init();
-        init_i8259_irqs();
-        bonito_irq_init();
-        /*
-        printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
-        printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n",
-                        BONITO_INTEN, BONITO_INTENSET,
-                        BONITO_INTENCLR, BONITO_INTISR);
-        */
-        /* bonito irq at IP2 */
-        setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
-        /* 8259 irq at IP5 */
-        setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
-}

diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c deleted file mode 100644 index 1d0a09f3b832..000000000000 --- a/arch/mips/lemote/lm2e/irq.c +++ /dev/null
@@ -1,143 +0,0 @@
1	/*
2	* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3	* Author: Fuxin Zhang, zhangfx@lemote.com
4	*
5	* This program is free software; you can redistribute it and/or modify it
6	* under the terms of the GNU General Public License as published by the
7	* Free Software Foundation; either version 2 of the License, or (at your
8	* option) any later version.
9	*
10	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20	*
21	* You should have received a copy of the GNU General Public License along
22	* with this program; if not, write to the Free Software Foundation, Inc.,
23	* 675 Mass Ave, Cambridge, MA 02139, USA.
24	*
25	*/
26	#include <linux/delay.h>
27	#include <linux/io.h>
28	#include <linux/init.h>
29	#include <linux/interrupt.h>
30	#include <linux/irq.h>
31
32	#include <asm/irq_cpu.h>
33	#include <asm/i8259.h>
34	#include <asm/mipsregs.h>
35	#include <asm/mips-boards/bonito64.h>
36
37
38	/*
39	* the first level int-handler will jump here if it is a bonito irq
40	*/
41	static void bonito_irqdispatch(void)
42	{
43	u32 int_status;
44	int i;
45
46	/* workaround the IO dma problem: let cpu looping to allow DMA finish */
47	int_status = BONITO_INTISR;
48	if (int_status & (1 << 10)) {
49	while (int_status & (1 << 10)) {
50	udelay(1);
51	int_status = BONITO_INTISR;
52	}
53	}
54
55	/* Get pending sources, masked by current enables */
56	int_status = BONITO_INTISR & BONITO_INTEN;
57
58	if (int_status != 0) {
59	i = __ffs(int_status);
60	int_status &= ~(1 << i);
61	do_IRQ(BONITO_IRQ_BASE + i);
62	}
63	}
64
65	static void i8259_irqdispatch(void)
66	{
67	int irq;
68
69	irq = i8259_irq();
70	if (irq >= 0) {
71	do_IRQ(irq);
72	} else {
73	spurious_interrupt();
74	}
75
76	}
77
78	asmlinkage void plat_irq_dispatch(void)
79	{
80	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
81
82	if (pending & CAUSEF_IP7) {
83	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
84	} else if (pending & CAUSEF_IP5) {
85	i8259_irqdispatch();
86	} else if (pending & CAUSEF_IP2) {
87	bonito_irqdispatch();
88	} else {
89	spurious_interrupt();
90	}
91	}
92
93	static struct irqaction cascade_irqaction = {
94	.handler = no_action,
95	.name = "cascade",
96	};
97
98	void __init arch_init_irq(void)
99	{
100	extern void bonito_irq_init(void);
101
102	/*
103	* Clear all of the interrupts while we change the able around a bit.
104	* int-handler is not on bootstrap
105	*/
106	clear_c0_status(ST0_IM \| ST0_BEV);
107	local_irq_disable();
108
109	/* most bonito irq should be level triggered */
110	BONITO_INTEDGE = BONITO_ICU_SYSTEMERR \| BONITO_ICU_MASTERERR \|
111	BONITO_ICU_RETRYERR \| BONITO_ICU_MBOXES;
112	BONITO_INTSTEER = 0;
113
114	/*
115	* Mask out all interrupt by writing "1" to all bit position in
116	* the interrupt reset reg.
117	*/
118	BONITO_INTENCLR = ~0;
119
120	/* init all controller
121	* 0-15 ------> i8259 interrupt
122	* 16-23 ------> mips cpu interrupt
123	* 32-63 ------> bonito irq
124	*/
125
126	/* Sets the first-level interrupt dispatcher. */
127	mips_cpu_irq_init();
128	init_i8259_irqs();
129	bonito_irq_init();
130
131	/*
132	printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
133	printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n",
134	BONITO_INTEN, BONITO_INTENSET,
135	BONITO_INTENCLR, BONITO_INTISR);
136	*/
137
138	/* bonito irq at IP2 */
139	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
140	/* 8259 irq at IP5 */
141	setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
142
143	}