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-rw-r--r--arch/mips/lantiq/falcon/sysctrl.c260
1 files changed, 260 insertions, 0 deletions
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
new file mode 100644
index 000000000000..ba0123d13d40
--- /dev/null
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -0,0 +1,260 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/ioport.h>
11#include <linux/export.h>
12#include <linux/clkdev.h>
13#include <linux/of_address.h>
14#include <asm/delay.h>
15
16#include <lantiq_soc.h>
17
18#include "../clk.h"
19
20/* infrastructure control register */
21#define SYS1_INFRAC 0x00bc
22/* Configuration fuses for drivers and pll */
23#define STATUS_CONFIG 0x0040
24
25/* GPE frequency selection */
26#define GPPC_OFFSET 24
27#define GPEFREQ_MASK 0x00000C0
28#define GPEFREQ_OFFSET 10
29/* Clock status register */
30#define SYSCTL_CLKS 0x0000
31/* Clock enable register */
32#define SYSCTL_CLKEN 0x0004
33/* Clock clear register */
34#define SYSCTL_CLKCLR 0x0008
35/* Activation Status Register */
36#define SYSCTL_ACTS 0x0020
37/* Activation Register */
38#define SYSCTL_ACT 0x0024
39/* Deactivation Register */
40#define SYSCTL_DEACT 0x0028
41/* reboot Register */
42#define SYSCTL_RBT 0x002c
43/* CPU0 Clock Control Register */
44#define SYS1_CPU0CC 0x0040
45/* HRST_OUT_N Control Register */
46#define SYS1_HRSTOUTC 0x00c0
47/* clock divider bit */
48#define CPU0CC_CPUDIV 0x0001
49
50/* Activation Status Register */
51#define ACTS_ASC1_ACT 0x00000800
52#define ACTS_I2C_ACT 0x00004000
53#define ACTS_P0 0x00010000
54#define ACTS_P1 0x00010000
55#define ACTS_P2 0x00020000
56#define ACTS_P3 0x00020000
57#define ACTS_P4 0x00040000
58#define ACTS_PADCTRL0 0x00100000
59#define ACTS_PADCTRL1 0x00100000
60#define ACTS_PADCTRL2 0x00200000
61#define ACTS_PADCTRL3 0x00200000
62#define ACTS_PADCTRL4 0x00400000
63
64#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
65#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
66#define sysctl_w32_mask(m, clear, set, reg) \
67 sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
68
69#define status_w32(x, y) ltq_w32((x), status_membase + (y))
70#define status_r32(x) ltq_r32(status_membase + (x))
71
72static void __iomem *sysctl_membase[3], *status_membase;
73void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
74
75void falcon_trigger_hrst(int level)
76{
77 sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
78}
79
80static inline void sysctl_wait(struct clk *clk,
81 unsigned int test, unsigned int reg)
82{
83 int err = 1000000;
84
85 do {} while (--err && ((sysctl_r32(clk->module, reg)
86 & clk->bits) != test));
87 if (!err)
88 pr_err("module de/activation failed %d %08X %08X %08X\n",
89 clk->module, clk->bits, test,
90 sysctl_r32(clk->module, reg) & clk->bits);
91}
92
93static int sysctl_activate(struct clk *clk)
94{
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
97 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
98 return 0;
99}
100
101static void sysctl_deactivate(struct clk *clk)
102{
103 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
104 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
105 sysctl_wait(clk, 0, SYSCTL_ACTS);
106}
107
108static int sysctl_clken(struct clk *clk)
109{
110 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
111 sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
112 return 0;
113}
114
115static void sysctl_clkdis(struct clk *clk)
116{
117 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
118 sysctl_wait(clk, 0, SYSCTL_CLKS);
119}
120
121static void sysctl_reboot(struct clk *clk)
122{
123 unsigned int act;
124 unsigned int bits;
125
126 act = sysctl_r32(clk->module, SYSCTL_ACT);
127 bits = ~act & clk->bits;
128 if (bits != 0) {
129 sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
130 sysctl_w32(clk->module, bits, SYSCTL_ACT);
131 sysctl_wait(clk, bits, SYSCTL_ACTS);
132 }
133 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
134 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
135}
136
137/* enable the ONU core */
138static void falcon_gpe_enable(void)
139{
140 unsigned int freq;
141 unsigned int status;
142
143 /* if if the clock is already enabled */
144 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
145 if (status & (1 << (GPPC_OFFSET + 1)))
146 return;
147
148 if (status_r32(STATUS_CONFIG) == 0)
149 freq = 1; /* use 625MHz on unfused chip */
150 else
151 freq = (status_r32(STATUS_CONFIG) &
152 GPEFREQ_MASK) >>
153 GPEFREQ_OFFSET;
154
155 /* apply new frequency */
156 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
157 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
158 udelay(1);
159
160 /* enable new frequency */
161 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
162 udelay(1);
163}
164
165static inline void clkdev_add_sys(const char *dev, unsigned int module,
166 unsigned int bits)
167{
168 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
169
170 clk->cl.dev_id = dev;
171 clk->cl.con_id = NULL;
172 clk->cl.clk = clk;
173 clk->module = module;
174 clk->activate = sysctl_activate;
175 clk->deactivate = sysctl_deactivate;
176 clk->enable = sysctl_clken;
177 clk->disable = sysctl_clkdis;
178 clk->reboot = sysctl_reboot;
179 clkdev_add(&clk->cl);
180}
181
182void __init ltq_soc_init(void)
183{
184 struct device_node *np_status =
185 of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
186 struct device_node *np_ebu =
187 of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
188 struct device_node *np_sys1 =
189 of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
190 struct device_node *np_syseth =
191 of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
192 struct device_node *np_sysgpe =
193 of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
194 struct resource res_status, res_ebu, res_sys[3];
195 int i;
196
197 /* check if all the core register ranges are available */
198 if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
199 panic("Failed to load core nodes from devicetree");
200
201 if (of_address_to_resource(np_status, 0, &res_status) ||
202 of_address_to_resource(np_ebu, 0, &res_ebu) ||
203 of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
204 of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
205 of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
206 panic("Failed to get core resources");
207
208 if ((request_mem_region(res_status.start, resource_size(&res_status),
209 res_status.name) < 0) ||
210 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
211 res_ebu.name) < 0) ||
212 (request_mem_region(res_sys[0].start,
213 resource_size(&res_sys[0]),
214 res_sys[0].name) < 0) ||
215 (request_mem_region(res_sys[1].start,
216 resource_size(&res_sys[1]),
217 res_sys[1].name) < 0) ||
218 (request_mem_region(res_sys[2].start,
219 resource_size(&res_sys[2]),
220 res_sys[2].name) < 0))
221 pr_err("Failed to request core reources");
222
223 status_membase = ioremap_nocache(res_status.start,
224 resource_size(&res_status));
225 ltq_ebu_membase = ioremap_nocache(res_ebu.start,
226 resource_size(&res_ebu));
227
228 if (!status_membase || !ltq_ebu_membase)
229 panic("Failed to remap core resources");
230
231 for (i = 0; i < 3; i++) {
232 sysctl_membase[i] = ioremap_nocache(res_sys[i].start,
233 resource_size(&res_sys[i]));
234 if (!sysctl_membase[i])
235 panic("Failed to remap sysctrl resources");
236 }
237 ltq_sys1_membase = sysctl_membase[0];
238
239 falcon_gpe_enable();
240
241 /* get our 3 static rates for cpu, fpi and io clocks */
242 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
243 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
244 else
245 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
246
247 /* add our clock domains */
248 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
249 clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
250 clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
251 clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
252 clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
253 clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
254 clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
255 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
256 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
257 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
258 clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
259 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
260}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 07:43:05 -0500