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-rw-r--r--arch/mips/kernel/bmips_vec.S3
-rw-r--r--arch/mips/kernel/branch.c8
-rw-r--r--arch/mips/kernel/cps-vec.S2
-rw-r--r--arch/mips/kernel/cpu-probe.c40
-rw-r--r--arch/mips/kernel/genex.S1
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/kernel/jump_label.c42
-rw-r--r--arch/mips/kernel/r2300_fpu.S6
-rw-r--r--arch/mips/kernel/r2300_switch.S5
-rw-r--r--arch/mips/kernel/r4k_fpu.S27
-rw-r--r--arch/mips/kernel/r4k_switch.S15
-rw-r--r--arch/mips/kernel/r6000_fpu.S5
-rw-r--r--arch/mips/kernel/rtlx.c4
-rw-r--r--arch/mips/kernel/scall32-o32.S1
-rw-r--r--arch/mips/kernel/scall64-64.S1
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/scall64-o32.S1
-rw-r--r--arch/mips/kernel/setup.c7
-rw-r--r--arch/mips/kernel/signal.c8
19 files changed, 143 insertions, 37 deletions
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index 290c23b51678..86495072a922 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -208,7 +208,6 @@ bmips_reset_nmi_vec_end:
208END(bmips_reset_nmi_vec) 208END(bmips_reset_nmi_vec)
209 209
210 .set pop 210 .set pop
211 .previous
212 211
213/*********************************************************************** 212/***********************************************************************
214 * CPU1 warm restart vector (used for second and subsequent boots). 213 * CPU1 warm restart vector (used for second and subsequent boots).
@@ -281,5 +280,3 @@ LEAF(bmips_enable_xks01)
281 jr ra 280 jr ra
282 281
283END(bmips_enable_xks01) 282END(bmips_enable_xks01)
284
285 .previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df224f041..4d7d99d601cc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
144 case mm_bc1t_op: 144 case mm_bc1t_op:
145 preempt_disable(); 145 preempt_disable();
146 if (is_fpu_owner()) 146 if (is_fpu_owner())
147 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 147 fcr31 = read_32bit_cp1_register(CP1_STATUS);
148 else 148 else
149 fcr31 = current->thread.fpu.fcr31; 149 fcr31 = current->thread.fpu.fcr31;
150 preempt_enable(); 150 preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
562 case cop1_op: 562 case cop1_op:
563 preempt_disable(); 563 preempt_disable();
564 if (is_fpu_owner()) 564 if (is_fpu_owner())
565 asm volatile( 565 fcr31 = read_32bit_cp1_register(CP1_STATUS);
566 ".set push\n"
567 "\t.set mips1\n"
568 "\tcfc1\t%0,$31\n"
569 "\t.set pop" : "=r" (fcr31));
570 else 566 else
571 fcr31 = current->thread.fpu.fcr31; 567 fcr31 = current->thread.fpu.fcr31;
572 preempt_enable(); 568 preempt_enable();
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index e6e97d2a5c9e..0384b05ab5a0 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -229,6 +229,7 @@ LEAF(mips_cps_core_init)
229 nop 229 nop
230 230
231 .set push 231 .set push
232 .set mips32r2
232 .set mt 233 .set mt
233 234
234 /* Only allow 1 TC per VPE to execute... */ 235 /* Only allow 1 TC per VPE to execute... */
@@ -345,6 +346,7 @@ LEAF(mips_cps_boot_vpes)
345 nop 346 nop
346 347
347 .set push 348 .set push
349 .set mips32r2
348 .set mt 350 .set mt
349 351
3501: /* Enter VPE configuration state */ 3521: /* Enter VPE configuration state */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 94c4a0c0a577..dc49cf30c2db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -193,6 +193,32 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
193static char unknown_isa[] = KERN_ERR \ 193static char unknown_isa[] = KERN_ERR \
194 "Unsupported ISA type, c0.config0: %d."; 194 "Unsupported ISA type, c0.config0: %d.";
195 195
196static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
197{
198
199 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
200
201 /*
202 * 0 = All TLBWR instructions go to FTLB
203 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
204 * FTLB and 1 goes to the VTLB.
205 * 2 = 7:1: As above with 7:1 ratio.
206 * 3 = 3:1: As above with 3:1 ratio.
207 *
208 * Use the linear midpoint as the probability threshold.
209 */
210 if (probability >= 12)
211 return 1;
212 else if (probability >= 6)
213 return 2;
214 else
215 /*
216 * So FTLB is less than 4 times bigger than VTLB.
217 * A 3:1 ratio can still be useful though.
218 */
219 return 3;
220}
221
196static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 222static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
197{ 223{
198 unsigned int config6; 224 unsigned int config6;
@@ -203,9 +229,14 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
203 case CPU_P5600: 229 case CPU_P5600:
204 /* proAptiv & related cores use Config6 to enable the FTLB */ 230 /* proAptiv & related cores use Config6 to enable the FTLB */
205 config6 = read_c0_config6(); 231 config6 = read_c0_config6();
232 /* Clear the old probability value */
233 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
206 if (enable) 234 if (enable)
207 /* Enable FTLB */ 235 /* Enable FTLB */
208 write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 236 write_c0_config6(config6 |
237 (calculate_ftlb_probability(c)
238 << MIPS_CONF6_FTLBP_SHIFT)
239 | MIPS_CONF6_FTLBEN);
209 else 240 else
210 /* Disable FTLB */ 241 /* Disable FTLB */
211 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 242 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
@@ -757,31 +788,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
757 c->cputype = CPU_LOONGSON2; 788 c->cputype = CPU_LOONGSON2;
758 __cpu_name[cpu] = "ICT Loongson-2"; 789 __cpu_name[cpu] = "ICT Loongson-2";
759 set_elf_platform(cpu, "loongson2e"); 790 set_elf_platform(cpu, "loongson2e");
791 set_isa(c, MIPS_CPU_ISA_III);
760 break; 792 break;
761 case PRID_REV_LOONGSON2F: 793 case PRID_REV_LOONGSON2F:
762 c->cputype = CPU_LOONGSON2; 794 c->cputype = CPU_LOONGSON2;
763 __cpu_name[cpu] = "ICT Loongson-2"; 795 __cpu_name[cpu] = "ICT Loongson-2";
764 set_elf_platform(cpu, "loongson2f"); 796 set_elf_platform(cpu, "loongson2f");
797 set_isa(c, MIPS_CPU_ISA_III);
765 break; 798 break;
766 case PRID_REV_LOONGSON3A: 799 case PRID_REV_LOONGSON3A:
767 c->cputype = CPU_LOONGSON3; 800 c->cputype = CPU_LOONGSON3;
768 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
769 __cpu_name[cpu] = "ICT Loongson-3"; 801 __cpu_name[cpu] = "ICT Loongson-3";
770 set_elf_platform(cpu, "loongson3a"); 802 set_elf_platform(cpu, "loongson3a");
803 set_isa(c, MIPS_CPU_ISA_M64R1);
771 break; 804 break;
772 case PRID_REV_LOONGSON3B_R1: 805 case PRID_REV_LOONGSON3B_R1:
773 case PRID_REV_LOONGSON3B_R2: 806 case PRID_REV_LOONGSON3B_R2:
774 c->cputype = CPU_LOONGSON3; 807 c->cputype = CPU_LOONGSON3;
775 __cpu_name[cpu] = "ICT Loongson-3"; 808 __cpu_name[cpu] = "ICT Loongson-3";
776 set_elf_platform(cpu, "loongson3b"); 809 set_elf_platform(cpu, "loongson3b");
810 set_isa(c, MIPS_CPU_ISA_M64R1);
777 break; 811 break;
778 } 812 }
779 813
780 set_isa(c, MIPS_CPU_ISA_III);
781 c->options = R4K_OPTS | 814 c->options = R4K_OPTS |
782 MIPS_CPU_FPU | MIPS_CPU_LLSC | 815 MIPS_CPU_FPU | MIPS_CPU_LLSC |
783 MIPS_CPU_32FPR; 816 MIPS_CPU_32FPR;
784 c->tlbsize = 64; 817 c->tlbsize = 64;
818 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
785 break; 819 break;
786 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 820 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
787 decode_configs(c); 821 decode_configs(c);
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac35e12cb1f3..a5e26dd90592 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
358 .set push 358 .set push
359 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 359 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
360 .set mips1 360 .set mips1
361 SET_HARDFLOAT
361 cfc1 a1, fcr31 362 cfc1 a1, fcr31
362 li a2, ~(0x3f << 12) 363 li a2, ~(0x3f << 12)
363 and a2, a1 364 and a2, a1
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 09ce45980758..0b9082b6b683 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -68,9 +68,6 @@ void r4k_wait_irqoff(void)
68 " wait \n" 68 " wait \n"
69 " .set pop \n"); 69 " .set pop \n");
70 local_irq_enable(); 70 local_irq_enable();
71 __asm__(
72 " .globl __pastwait \n"
73 "__pastwait: \n");
74} 71}
75 72
76/* 73/*
diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c
index 6001610cfe55..dda800e9e731 100644
--- a/arch/mips/kernel/jump_label.c
+++ b/arch/mips/kernel/jump_label.c
@@ -18,31 +18,53 @@
18 18
19#ifdef HAVE_JUMP_LABEL 19#ifdef HAVE_JUMP_LABEL
20 20
21#define J_RANGE_MASK ((1ul << 28) - 1) 21/*
22 * Define parameters for the standard MIPS and the microMIPS jump
23 * instruction encoding respectively:
24 *
25 * - the ISA bit of the target, either 0 or 1 respectively,
26 *
27 * - the amount the jump target address is shifted right to fit in the
28 * immediate field of the machine instruction, either 2 or 1,
29 *
30 * - the mask determining the size of the jump region relative to the
31 * delay-slot instruction, either 256MB or 128MB,
32 *
33 * - the jump target alignment, either 4 or 2 bytes.
34 */
35#define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS)
36#define J_RANGE_SHIFT (2 - J_ISA_BIT)
37#define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
38#define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
22 39
23void arch_jump_label_transform(struct jump_entry *e, 40void arch_jump_label_transform(struct jump_entry *e,
24 enum jump_label_type type) 41 enum jump_label_type type)
25{ 42{
43 union mips_instruction *insn_p;
26 union mips_instruction insn; 44 union mips_instruction insn;
27 union mips_instruction *insn_p =
28 (union mips_instruction *)(unsigned long)e->code;
29 45
30 /* Jump only works within a 256MB aligned region. */ 46 insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
31 BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK)); 47
48 /* Jump only works within an aligned region its delay slot is in. */
49 BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
32 50
33 /* Target must have 4 byte alignment. */ 51 /* Target must have the right alignment and ISA must be preserved. */
34 BUG_ON((e->target & 3) != 0); 52 BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
35 53
36 if (type == JUMP_LABEL_ENABLE) { 54 if (type == JUMP_LABEL_ENABLE) {
37 insn.j_format.opcode = j_op; 55 insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
38 insn.j_format.target = (e->target & J_RANGE_MASK) >> 2; 56 insn.j_format.target = e->target >> J_RANGE_SHIFT;
39 } else { 57 } else {
40 insn.word = 0; /* nop */ 58 insn.word = 0; /* nop */
41 } 59 }
42 60
43 get_online_cpus(); 61 get_online_cpus();
44 mutex_lock(&text_mutex); 62 mutex_lock(&text_mutex);
45 *insn_p = insn; 63 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
64 insn_p->halfword[0] = insn.word >> 16;
65 insn_p->halfword[1] = insn.word;
66 } else
67 *insn_p = insn;
46 68
47 flush_icache_range((unsigned long)insn_p, 69 flush_icache_range((unsigned long)insn_p,
48 (unsigned long)insn_p + sizeof(*insn_p)); 70 (unsigned long)insn_p + sizeof(*insn_p));
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index f31063dbdaeb..5ce3b746cedc 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
28 .set mips1 28 .set mips1
29 /* Save floating point context */ 29 /* Save floating point context */
30LEAF(_save_fp_context) 30LEAF(_save_fp_context)
31 .set push
32 SET_HARDFLOAT
31 li v0, 0 # assume success 33 li v0, 0 # assume success
32 cfc1 t1,fcr31 34 cfc1 t1,fcr31
33 EX(swc1 $f0,(SC_FPREGS+0)(a0)) 35 EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
65 EX(sw t1,(SC_FPC_CSR)(a0)) 67 EX(sw t1,(SC_FPC_CSR)(a0))
66 cfc1 t0,$0 # implementation/version 68 cfc1 t0,$0 # implementation/version
67 jr ra 69 jr ra
70 .set pop
68 .set nomacro 71 .set nomacro
69 EX(sw t0,(SC_FPC_EIR)(a0)) 72 EX(sw t0,(SC_FPC_EIR)(a0))
70 .set macro 73 .set macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
80 * stack frame which might have been changed by the user. 83 * stack frame which might have been changed by the user.
81 */ 84 */
82LEAF(_restore_fp_context) 85LEAF(_restore_fp_context)
86 .set push
87 SET_HARDFLOAT
83 li v0, 0 # assume success 88 li v0, 0 # assume success
84 EX(lw t0,(SC_FPC_CSR)(a0)) 89 EX(lw t0,(SC_FPC_CSR)(a0))
85 EX(lwc1 $f0,(SC_FPREGS+0)(a0)) 90 EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
116 EX(lwc1 $f31,(SC_FPREGS+248)(a0)) 121 EX(lwc1 $f31,(SC_FPREGS+248)(a0))
117 jr ra 122 jr ra
118 ctc1 t0,fcr31 123 ctc1 t0,fcr31
124 .set pop
119 END(_restore_fp_context) 125 END(_restore_fp_context)
120 .set reorder 126 .set reorder
121 127
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 20b7b040e76f..435ea652f5fa 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
120 120
121#define FPU_DEFAULT 0x00000000 121#define FPU_DEFAULT 0x00000000
122 122
123 .set push
124 SET_HARDFLOAT
125
123LEAF(_init_fpu) 126LEAF(_init_fpu)
124 mfc0 t0, CP0_STATUS 127 mfc0 t0, CP0_STATUS
125 li t1, ST0_CU1 128 li t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
165 mtc1 t0, $f31 168 mtc1 t0, $f31
166 jr ra 169 jr ra
167 END(_init_fpu) 170 END(_init_fpu)
171
172 .set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8352523568e6..6c160c67984c 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/regdef.h> 20#include <asm/regdef.h>
21 21
22/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
23#undef fp
24
22 .macro EX insn, reg, src 25 .macro EX insn, reg, src
23 .set push 26 .set push
27 SET_HARDFLOAT
24 .set nomacro 28 .set nomacro
25.ex\@: \insn \reg, \src 29.ex\@: \insn \reg, \src
26 .set pop 30 .set pop
@@ -33,12 +37,17 @@
33 .set arch=r4000 37 .set arch=r4000
34 38
35LEAF(_save_fp_context) 39LEAF(_save_fp_context)
40 .set push
41 SET_HARDFLOAT
36 cfc1 t1, fcr31 42 cfc1 t1, fcr31
43 .set pop
37 44
38#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 45#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
39 .set push 46 .set push
47 SET_HARDFLOAT
40#ifdef CONFIG_CPU_MIPS32_R2 48#ifdef CONFIG_CPU_MIPS32_R2
41 .set mips64r2 49 .set mips32r2
50 .set fp=64
42 mfc0 t0, CP0_STATUS 51 mfc0 t0, CP0_STATUS
43 sll t0, t0, 5 52 sll t0, t0, 5
44 bgez t0, 1f # skip storing odd if FR=0 53 bgez t0, 1f # skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
641: .set pop 731: .set pop
65#endif 74#endif
66 75
76 .set push
77 SET_HARDFLOAT
67 /* Store the 16 even double precision registers */ 78 /* Store the 16 even double precision registers */
68 EX sdc1 $f0, SC_FPREGS+0(a0) 79 EX sdc1 $f0, SC_FPREGS+0(a0)
69 EX sdc1 $f2, SC_FPREGS+16(a0) 80 EX sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
84 EX sw t1, SC_FPC_CSR(a0) 95 EX sw t1, SC_FPC_CSR(a0)
85 jr ra 96 jr ra
86 li v0, 0 # success 97 li v0, 0 # success
98 .set pop
87 END(_save_fp_context) 99 END(_save_fp_context)
88 100
89#ifdef CONFIG_MIPS32_COMPAT 101#ifdef CONFIG_MIPS32_COMPAT
90 /* Save 32-bit process floating point context */ 102 /* Save 32-bit process floating point context */
91LEAF(_save_fp_context32) 103LEAF(_save_fp_context32)
104 .set push
105 SET_HARDFLOAT
92 cfc1 t1, fcr31 106 cfc1 t1, fcr31
93 107
94 mfc0 t0, CP0_STATUS 108 mfc0 t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
134 EX sw t1, SC32_FPC_CSR(a0) 148 EX sw t1, SC32_FPC_CSR(a0)
135 cfc1 t0, $0 # implementation/version 149 cfc1 t0, $0 # implementation/version
136 EX sw t0, SC32_FPC_EIR(a0) 150 EX sw t0, SC32_FPC_EIR(a0)
151 .set pop
137 152
138 jr ra 153 jr ra
139 li v0, 0 # success 154 li v0, 0 # success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
150 165
151#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 166#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
152 .set push 167 .set push
168 SET_HARDFLOAT
153#ifdef CONFIG_CPU_MIPS32_R2 169#ifdef CONFIG_CPU_MIPS32_R2
154 .set mips64r2 170 .set mips32r2
171 .set fp=64
155 mfc0 t0, CP0_STATUS 172 mfc0 t0, CP0_STATUS
156 sll t0, t0, 5 173 sll t0, t0, 5
157 bgez t0, 1f # skip loading odd if FR=0 174 bgez t0, 1f # skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
175 EX ldc1 $f31, SC_FPREGS+248(a0) 192 EX ldc1 $f31, SC_FPREGS+248(a0)
1761: .set pop 1931: .set pop
177#endif 194#endif
195 .set push
196 SET_HARDFLOAT
178 EX ldc1 $f0, SC_FPREGS+0(a0) 197 EX ldc1 $f0, SC_FPREGS+0(a0)
179 EX ldc1 $f2, SC_FPREGS+16(a0) 198 EX ldc1 $f2, SC_FPREGS+16(a0)
180 EX ldc1 $f4, SC_FPREGS+32(a0) 199 EX ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
192 EX ldc1 $f28, SC_FPREGS+224(a0) 211 EX ldc1 $f28, SC_FPREGS+224(a0)
193 EX ldc1 $f30, SC_FPREGS+240(a0) 212 EX ldc1 $f30, SC_FPREGS+240(a0)
194 ctc1 t1, fcr31 213 ctc1 t1, fcr31
214 .set pop
195 jr ra 215 jr ra
196 li v0, 0 # success 216 li v0, 0 # success
197 END(_restore_fp_context) 217 END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
199#ifdef CONFIG_MIPS32_COMPAT 219#ifdef CONFIG_MIPS32_COMPAT
200LEAF(_restore_fp_context32) 220LEAF(_restore_fp_context32)
201 /* Restore an o32 sigcontext. */ 221 /* Restore an o32 sigcontext. */
222 .set push
223 SET_HARDFLOAT
202 EX lw t1, SC32_FPC_CSR(a0) 224 EX lw t1, SC32_FPC_CSR(a0)
203 225
204 mfc0 t0, CP0_STATUS 226 mfc0 t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
242 ctc1 t1, fcr31 264 ctc1 t1, fcr31
243 jr ra 265 jr ra
244 li v0, 0 # success 266 li v0, 0 # success
267 .set pop
245 END(_restore_fp_context32) 268 END(_restore_fp_context32)
246#endif 269#endif
247 270
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 4c4ec1812420..64591e671878 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
22 22
23#include <asm/asmmacro.h> 23#include <asm/asmmacro.h>
24 24
25/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
26#undef fp
27
25/* 28/*
26 * Offset to the current process status flags, the first 32 bytes of the 29 * Offset to the current process status flags, the first 32 bytes of the
27 * stack are not used. 30 * stack are not used.
@@ -65,8 +68,12 @@
65 bgtz a3, 1f 68 bgtz a3, 1f
66 69
67 /* Save 128b MSA vector context + scalar FP control & status. */ 70 /* Save 128b MSA vector context + scalar FP control & status. */
71 .set push
72 SET_HARDFLOAT
68 cfc1 t1, fcr31 73 cfc1 t1, fcr31
69 msa_save_all a0 74 msa_save_all a0
75 .set pop /* SET_HARDFLOAT */
76
70 sw t1, THREAD_FCR31(a0) 77 sw t1, THREAD_FCR31(a0)
71 b 2f 78 b 2f
72 79
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
161 168
162#define FPU_DEFAULT 0x00000000 169#define FPU_DEFAULT 0x00000000
163 170
171 .set push
172 SET_HARDFLOAT
173
164LEAF(_init_fpu) 174LEAF(_init_fpu)
165 mfc0 t0, CP0_STATUS 175 mfc0 t0, CP0_STATUS
166 li t1, ST0_CU1 176 li t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
232 242
233#ifdef CONFIG_CPU_MIPS32_R2 243#ifdef CONFIG_CPU_MIPS32_R2
234 .set push 244 .set push
235 .set mips64r2 245 .set mips32r2
246 .set fp=64
236 sll t0, t0, 5 # is Status.FR set? 247 sll t0, t0, 5 # is Status.FR set?
237 bgez t0, 1f # no: skip setting upper 32b 248 bgez t0, 1f # no: skip setting upper 32b
238 249
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
291#endif 302#endif
292 jr ra 303 jr ra
293 END(_init_fpu) 304 END(_init_fpu)
305
306 .set pop /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index da0fbe46d83b..47077380c15c 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
18 18
19 .set noreorder 19 .set noreorder
20 .set mips2 20 .set mips2
21 .set push
22 SET_HARDFLOAT
23
21 /* Save floating point context */ 24 /* Save floating point context */
22 LEAF(_save_fp_context) 25 LEAF(_save_fp_context)
23 mfc0 t0,CP0_STATUS 26 mfc0 t0,CP0_STATUS
@@ -85,3 +88,5 @@
851: jr ra 881: jr ra
86 nop 89 nop
87 END(_restore_fp_context) 90 END(_restore_fp_context)
91
92 .set pop /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 31b1b763cb29..c5c4fd54d797 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -94,12 +94,12 @@ int rtlx_open(int index, int can_sleep)
94 int ret = 0; 94 int ret = 0;
95 95
96 if (index >= RTLX_CHANNELS) { 96 if (index >= RTLX_CHANNELS) {
97 pr_debug(KERN_DEBUG "rtlx_open index out of range\n"); 97 pr_debug("rtlx_open index out of range\n");
98 return -ENOSYS; 98 return -ENOSYS;
99 } 99 }
100 100
101 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { 101 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) {
102 pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index); 102 pr_debug("rtlx_open channel %d already opened\n", index);
103 ret = -EBUSY; 103 ret = -EBUSY;
104 goto out_fail; 104 goto out_fail;
105 } 105 }
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 744cd10ba599..00cad1005a16 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -579,3 +579,4 @@ EXPORT(sys_call_table)
579 PTR sys_seccomp 579 PTR sys_seccomp
580 PTR sys_getrandom 580 PTR sys_getrandom
581 PTR sys_memfd_create 581 PTR sys_memfd_create
582 PTR sys_bpf /* 4355 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 002b1bc09c38..5251565e344b 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -434,4 +434,5 @@ EXPORT(sys_call_table)
434 PTR sys_seccomp 434 PTR sys_seccomp
435 PTR sys_getrandom 435 PTR sys_getrandom
436 PTR sys_memfd_create 436 PTR sys_memfd_create
437 PTR sys_bpf /* 5315 */
437 .size sys_call_table,.-sys_call_table 438 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ca6cbbe9805b..77e74398b828 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -427,4 +427,5 @@ EXPORT(sysn32_call_table)
427 PTR sys_seccomp 427 PTR sys_seccomp
428 PTR sys_getrandom 428 PTR sys_getrandom
429 PTR sys_memfd_create 429 PTR sys_memfd_create
430 PTR sys_bpf
430 .size sysn32_call_table,.-sysn32_call_table 431 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9e10d11fbb84..6f8db9f728e8 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -564,4 +564,5 @@ EXPORT(sys32_call_table)
564 PTR sys_seccomp 564 PTR sys_seccomp
565 PTR sys_getrandom 565 PTR sys_getrandom
566 PTR sys_memfd_create 566 PTR sys_memfd_create
567 PTR sys_bpf /* 4355 */
567 .size sys32_call_table,.-sys32_call_table 568 .size sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b3b8f0d9d4a7..f3b635f86c39 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -485,7 +485,7 @@ static void __init bootmem_init(void)
485 * NOTE: historically plat_mem_setup did the entire platform initialization. 485 * NOTE: historically plat_mem_setup did the entire platform initialization.
486 * This was rather impractical because it meant plat_mem_setup had to 486 * This was rather impractical because it meant plat_mem_setup had to
487 * get away without any kind of memory allocator. To keep old code from 487 * get away without any kind of memory allocator. To keep old code from
488 * breaking plat_setup was just renamed to plat_setup and a second platform 488 * breaking plat_setup was just renamed to plat_mem_setup and a second platform
489 * initialization hook for anything else was introduced. 489 * initialization hook for anything else was introduced.
490 */ 490 */
491 491
@@ -493,7 +493,7 @@ static int usermem __initdata;
493 493
494static int __init early_parse_mem(char *p) 494static int __init early_parse_mem(char *p)
495{ 495{
496 unsigned long start, size; 496 phys_t start, size;
497 497
498 /* 498 /*
499 * If a user specifies memory size, we 499 * If a user specifies memory size, we
@@ -683,7 +683,8 @@ static void __init arch_mem_init(char **cmdline_p)
683 dma_contiguous_reserve(PFN_PHYS(max_low_pfn)); 683 dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
684 /* Tell bootmem about cma reserved memblock section */ 684 /* Tell bootmem about cma reserved memblock section */
685 for_each_memblock(reserved, reg) 685 for_each_memblock(reserved, reg)
686 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT); 686 if (reg->size != 0)
687 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
687} 688}
688 689
689static void __init resource_init(void) 690static void __init resource_init(void)
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 1d57605e4615..16f1e4f2bf3c 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -658,13 +658,13 @@ static int signal_setup(void)
658 save_fp_context = _save_fp_context; 658 save_fp_context = _save_fp_context;
659 restore_fp_context = _restore_fp_context; 659 restore_fp_context = _restore_fp_context;
660 } else { 660 } else {
661 save_fp_context = copy_fp_from_sigcontext; 661 save_fp_context = copy_fp_to_sigcontext;
662 restore_fp_context = copy_fp_to_sigcontext; 662 restore_fp_context = copy_fp_from_sigcontext;
663 } 663 }
664#endif /* CONFIG_SMP */ 664#endif /* CONFIG_SMP */
665#else 665#else
666 save_fp_context = copy_fp_from_sigcontext;; 666 save_fp_context = copy_fp_to_sigcontext;
667 restore_fp_context = copy_fp_to_sigcontext; 667 restore_fp_context = copy_fp_from_sigcontext;
668#endif 668#endif
669 669
670 return 0; 670 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-02 16:42:38 -0400