12 files changed, 64 insertions, 10 deletions

diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df224f041..4d7d99d601cc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                 case mm_bc1t_op:
                         preempt_disable();
                         if (is_fpu_owner())
-                                asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+                                fcr31 = read_32bit_cp1_register(CP1_STATUS);
                         else
                                 fcr31 = current->thread.fpu.fcr31;
                         preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
         case cop1_op:
                 preempt_disable();
                 if (is_fpu_owner())
-                        asm volatile(
-                                ".set push\n"
-                                "\t.set mips1\n"
-                                "\tcfc1\t%0,$31\n"
-                                "\t.set pop" : "=r" (fcr31));
+                        fcr31 = read_32bit_cp1_register(CP1_STATUS);
                 else
                         fcr31 = current->thread.fpu.fcr31;
                 preempt_enable();
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac35e12cb1f3..a5e26dd90592 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
         .set    push
         /* gas fails to assemble cfc1 for some archs (octeon).*/ \
         .set    mips1
+        SET_HARDFLOAT
         cfc1    a1, fcr31
         li      a2, ~(0x3f << 12)
         and     a2, a1
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index f31063dbdaeb..5ce3b746cedc 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
         .set    mips1
         /* Save floating point context */
 LEAF(_save_fp_context)
+        .set    push
+        SET_HARDFLOAT
         li      v0, 0                                   # assume success
         cfc1    t1,fcr31
         EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
         EX(sw   t1,(SC_FPC_CSR)(a0))
         cfc1    t0,$0                           # implementation/version
         jr      ra
+        .set    pop
         .set    nomacro
          EX(sw  t0,(SC_FPC_EIR)(a0))
         .set    macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
  * stack frame which might have been changed by the user.
  */
 LEAF(_restore_fp_context)
+        .set    push
+        SET_HARDFLOAT
         li      v0, 0                                   # assume success
         EX(lw t0,(SC_FPC_CSR)(a0))
         EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
         EX(lwc1 $f31,(SC_FPREGS+248)(a0))
         jr      ra
          ctc1   t0,fcr31
+        .set    pop
         END(_restore_fp_context)
         .set    reorder
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 20b7b040e76f..435ea652f5fa 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+        .set push
+        SET_HARDFLOAT
+
 LEAF(_init_fpu)
         mfc0    t0, CP0_STATUS
         li      t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
         mtc1    t0, $f31
         jr      ra
         END(_init_fpu)
+
+        .set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8352523568e6..6c160c67984c 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
         .macro  EX insn, reg, src
         .set    push
+        SET_HARDFLOAT
         .set    nomacro
 .ex\@:  \insn   \reg, \src
         .set    pop
@@ -33,12 +37,17 @@
         .set    arch=r4000
 
 LEAF(_save_fp_context)
+        .set    push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
+        .set    pop
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         .set    push
+        SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         mfc0    t0, CP0_STATUS
         sll     t0, t0, 5
         bgez    t0, 1f                  # skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
 1:      .set    pop
 #endif
 
+        .set push
+        SET_HARDFLOAT
         /* Store the 16 even double precision registers */
         EX      sdc1 $f0, SC_FPREGS+0(a0)
         EX      sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
         EX      sw t1, SC_FPC_CSR(a0)
         jr      ra
          li     v0, 0                                   # success
+        .set pop
         END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
         /* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
+        .set push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
 
         mfc0    t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
         EX      sw t1, SC32_FPC_CSR(a0)
         cfc1    t0, $0                          # implementation/version
         EX      sw t0, SC32_FPC_EIR(a0)
+        .set pop
 
         jr      ra
          li     v0, 0                                   # success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         .set    push
+        SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         mfc0    t0, CP0_STATUS
         sll     t0, t0, 5
         bgez    t0, 1f                  # skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
         EX      ldc1 $f31, SC_FPREGS+248(a0)
 1:      .set pop
 #endif
+        .set push
+        SET_HARDFLOAT
         EX      ldc1 $f0, SC_FPREGS+0(a0)
         EX      ldc1 $f2, SC_FPREGS+16(a0)
         EX      ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
         EX      ldc1 $f28, SC_FPREGS+224(a0)
         EX      ldc1 $f30, SC_FPREGS+240(a0)
         ctc1    t1, fcr31
+        .set pop
         jr      ra
          li     v0, 0                                   # success
         END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 LEAF(_restore_fp_context32)
         /* Restore an o32 sigcontext.  */
+        .set push
+        SET_HARDFLOAT
         EX      lw t1, SC32_FPC_CSR(a0)
 
         mfc0    t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
         ctc1    t1, fcr31
         jr      ra
          li     v0, 0                                   # success
+        .set pop
         END(_restore_fp_context32)
 #endif
 
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 4c4ec1812420..64591e671878 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
 
 #include <asm/asmmacro.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
@@ -65,8 +68,12 @@
         bgtz    a3, 1f
 
         /* Save 128b MSA vector context + scalar FP control & status. */
+        .set push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
         msa_save_all    a0
+        .set pop        /* SET_HARDFLOAT */
+
         sw      t1, THREAD_FCR31(a0)
         b       2f
 
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
 
 #define FPU_DEFAULT  0x00000000
 
+        .set push
+        SET_HARDFLOAT
+
 LEAF(_init_fpu)
         mfc0    t0, CP0_STATUS
         li      t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
 
 #ifdef CONFIG_CPU_MIPS32_R2
         .set    push
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         sll     t0, t0, 5                       # is Status.FR set?
         bgez    t0, 1f                          # no: skip setting upper 32b
 
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
 #endif
         jr      ra
         END(_init_fpu)
+
+        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index da0fbe46d83b..47077380c15c 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
 
         .set    noreorder
         .set    mips2
+        .set    push
+        SET_HARDFLOAT
+
         /* Save floating point context */
         LEAF(_save_fp_context)
         mfc0    t0,CP0_STATUS
@@ -85,3 +88,5 @@
 1:      jr      ra
          nop
         END(_restore_fp_context)
+
+        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 744cd10ba599..00cad1005a16 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -579,3 +579,4 @@ EXPORT(sys_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 4355 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 002b1bc09c38..5251565e344b 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -434,4 +434,5 @@ EXPORT(sys_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 5315 */
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ca6cbbe9805b..77e74398b828 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -427,4 +427,5 @@ EXPORT(sysn32_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9e10d11fbb84..6f8db9f728e8 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -564,4 +564,5 @@ EXPORT(sys32_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 4355 */
         .size   sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b3b8f0d9d4a7..d21ec57b6e95 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -683,7 +683,8 @@ static void __init arch_mem_init(char **cmdline_p)
         dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
         /* Tell bootmem about cma reserved memblock section */
         for_each_memblock(reserved, reg)
-                reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+                if (reg->size != 0)
+                        reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
 }
 
 static void __init resource_init(void)