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-rw-r--r--arch/mips/kernel/Makefile4
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c10
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c10
-rw-r--r--arch/mips/kernel/bmips_vec.S6
-rw-r--r--arch/mips/kernel/branch.c10
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c4
-rw-r--r--arch/mips/kernel/cevt-ds1287.c4
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c4
-rw-r--r--arch/mips/kernel/cevt-r4k.c6
-rw-r--r--arch/mips/kernel/cevt-sb1250.c4
-rw-r--r--arch/mips/kernel/cevt-smtc.c2
-rw-r--r--arch/mips/kernel/cevt-txx9.c6
-rw-r--r--arch/mips/kernel/cpu-bugs64.c10
-rw-r--r--arch/mips/kernel/cpu-probe.c30
-rw-r--r--arch/mips/kernel/cpufreq/loongson2_cpufreq.c4
-rw-r--r--arch/mips/kernel/crash.c2
-rw-r--r--arch/mips/kernel/csrc-bcm1480.c2
-rw-r--r--arch/mips/kernel/csrc-ioasic.c2
-rw-r--r--arch/mips/kernel/csrc-powertv.c6
-rw-r--r--arch/mips/kernel/csrc-sb1250.c2
-rw-r--r--arch/mips/kernel/ftrace.c12
-rw-r--r--arch/mips/kernel/genex.S14
-rw-r--r--arch/mips/kernel/head.S4
-rw-r--r--arch/mips/kernel/i8259.c2
-rw-r--r--arch/mips/kernel/irq-gt641xx.c4
-rw-r--r--arch/mips/kernel/irq-msc01.c6
-rw-r--r--arch/mips/kernel/irq-rm7000.c4
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/irq_cpu.c8
-rw-r--r--arch/mips/kernel/irq_txx9.c10
-rw-r--r--arch/mips/kernel/kgdb.c6
-rw-r--r--arch/mips/kernel/kprobes.c10
-rw-r--r--arch/mips/kernel/linux32.c12
-rw-r--r--arch/mips/kernel/mips_ksyms.c4
-rw-r--r--arch/mips/kernel/module-rela.c6
-rw-r--r--arch/mips/kernel/module.c10
-rw-r--r--arch/mips/kernel/octeon_switch.S104
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c30
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/process.c4
-rw-r--r--arch/mips/kernel/ptrace.c12
-rw-r--r--arch/mips/kernel/ptrace32.c2
-rw-r--r--arch/mips/kernel/r2300_fpu.S128
-rw-r--r--arch/mips/kernel/r2300_switch.S2
-rw-r--r--arch/mips/kernel/r4k_switch.S4
-rw-r--r--arch/mips/kernel/relocate_kernel.S12
-rw-r--r--arch/mips/kernel/rtlx.c18
-rw-r--r--arch/mips/kernel/scall32-o32.S14
-rw-r--r--arch/mips/kernel/scall64-64.S6
-rw-r--r--arch/mips/kernel/scall64-n32.S10
-rw-r--r--arch/mips/kernel/scall64-o32.S14
-rw-r--r--arch/mips/kernel/setup.c10
-rw-r--r--arch/mips/kernel/signal.c18
-rw-r--r--arch/mips/kernel/signal32.c24
-rw-r--r--arch/mips/kernel/signal_n32.c18
-rw-r--r--arch/mips/kernel/smp-cmp.c2
-rw-r--r--arch/mips/kernel/smp-mt.c4
-rw-r--r--arch/mips/kernel/smtc-asm.S2
-rw-r--r--arch/mips/kernel/smtc-proc.c6
-rw-r--r--arch/mips/kernel/smtc.c20
-rw-r--r--arch/mips/kernel/sync-r4k.c2
-rw-r--r--arch/mips/kernel/syscall.c6
-rw-r--r--arch/mips/kernel/time.c12
-rw-r--r--arch/mips/kernel/traps.c28
-rw-r--r--arch/mips/kernel/unaligned.c34
-rw-r--r--arch/mips/kernel/vmlinux.lds.S8
-rw-r--r--arch/mips/kernel/vpe.c98
-rw-r--r--arch/mips/kernel/watch.c4
68 files changed, 450 insertions, 450 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 007c33d73715..c48ed923fd55 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
39obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 39obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
40obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 40obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
41obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 41obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
42obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 42obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
43 43
44obj-$(CONFIG_SMP) += smp.o 44obj-$(CONFIG_SMP) += smp.o
45obj-$(CONFIG_SMP_UP) += smp-up.o 45obj-$(CONFIG_SMP_UP) += smp-up.o
@@ -53,7 +53,7 @@ obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
53obj-$(CONFIG_CPU_MIPSR2) += spram.o 53obj-$(CONFIG_CPU_MIPSR2) += spram.o
54 54
55obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 55obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
56obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 56obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
57 57
58obj-$(CONFIG_I8259) += i8259.o 58obj-$(CONFIG_I8259) += i8259.o
59obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 59obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index 9fdd8bcdd21e..e06f777e9c49 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -6,7 +6,7 @@
6 * 6 *
7 * Heavily inspired by the 32-bit Sparc compat code which is 7 * Heavily inspired by the 32-bit Sparc compat code which is
8 * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com) 8 * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)
9 * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz) 9 * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz)
10 */ 10 */
11 11
12#define ELF_ARCH EM_MIPS 12#define ELF_ARCH EM_MIPS
@@ -48,7 +48,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
48 48
49#define TASK32_SIZE 0x7fff8000UL 49#define TASK32_SIZE 0x7fff8000UL
50#undef ELF_ET_DYN_BASE 50#undef ELF_ET_DYN_BASE
51#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) 51#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2)
52 52
53#include <asm/processor.h> 53#include <asm/processor.h>
54#include <linux/module.h> 54#include <linux/module.h>
@@ -67,8 +67,8 @@ struct elf_prstatus32
67 pid_t pr_ppid; 67 pid_t pr_ppid;
68 pid_t pr_pgrp; 68 pid_t pr_pgrp;
69 pid_t pr_sid; 69 pid_t pr_sid;
70 struct compat_timeval pr_utime; /* User time */ 70 struct compat_timeval pr_utime; /* User time */
71 struct compat_timeval pr_stime; /* System time */ 71 struct compat_timeval pr_stime; /* System time */
72 struct compat_timeval pr_cutime;/* Cumulative user time */ 72 struct compat_timeval pr_cutime;/* Cumulative user time */
73 struct compat_timeval pr_cstime;/* Cumulative system time */ 73 struct compat_timeval pr_cstime;/* Cumulative system time */
74 elf_gregset_t pr_reg; /* GP registers */ 74 elf_gregset_t pr_reg; /* GP registers */
@@ -88,7 +88,7 @@ struct elf_prpsinfo32
88 pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; 88 pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid;
89 /* Lots missing */ 89 /* Lots missing */
90 char pr_fname[16]; /* filename of executable */ 90 char pr_fname[16]; /* filename of executable */
91 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ 91 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
92}; 92};
93 93
94#define elf_caddr_t u32 94#define elf_caddr_t u32
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index ff448233dab5..556a4357d7fc 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -6,7 +6,7 @@
6 * 6 *
7 * Heavily inspired by the 32-bit Sparc compat code which is 7 * Heavily inspired by the 32-bit Sparc compat code which is
8 * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com) 8 * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)
9 * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz) 9 * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz)
10 */ 10 */
11 11
12#define ELF_ARCH EM_MIPS 12#define ELF_ARCH EM_MIPS
@@ -50,7 +50,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
50 50
51#define TASK32_SIZE 0x7fff8000UL 51#define TASK32_SIZE 0x7fff8000UL
52#undef ELF_ET_DYN_BASE 52#undef ELF_ET_DYN_BASE
53#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) 53#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2)
54 54
55#include <asm/processor.h> 55#include <asm/processor.h>
56 56
@@ -86,8 +86,8 @@ struct elf_prstatus32
86 pid_t pr_ppid; 86 pid_t pr_ppid;
87 pid_t pr_pgrp; 87 pid_t pr_pgrp;
88 pid_t pr_sid; 88 pid_t pr_sid;
89 struct compat_timeval pr_utime; /* User time */ 89 struct compat_timeval pr_utime; /* User time */
90 struct compat_timeval pr_stime; /* System time */ 90 struct compat_timeval pr_stime; /* System time */
91 struct compat_timeval pr_cutime;/* Cumulative user time */ 91 struct compat_timeval pr_cutime;/* Cumulative user time */
92 struct compat_timeval pr_cstime;/* Cumulative system time */ 92 struct compat_timeval pr_cstime;/* Cumulative system time */
93 elf_gregset_t pr_reg; /* GP registers */ 93 elf_gregset_t pr_reg; /* GP registers */
@@ -107,7 +107,7 @@ struct elf_prpsinfo32
107 pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; 107 pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid;
108 /* Lots missing */ 108 /* Lots missing */
109 char pr_fname[16]; /* filename of executable */ 109 char pr_fname[16]; /* filename of executable */
110 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ 110 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
111}; 111};
112 112
113#define elf_caddr_t u32 113#define elf_caddr_t u32
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index e908e81330b1..64c4fd62cf08 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -170,7 +170,7 @@ bmips_smp_entry:
170 170
171 /* switch to permanent stack and continue booting */ 171 /* switch to permanent stack and continue booting */
172 172
173 .global bmips_secondary_reentry 173 .global bmips_secondary_reentry
174bmips_secondary_reentry: 174bmips_secondary_reentry:
175 la k0, bmips_smp_boot_sp 175 la k0, bmips_smp_boot_sp
176 lw sp, 0(k0) 176 lw sp, 0(k0)
@@ -182,7 +182,7 @@ bmips_secondary_reentry:
182#endif /* CONFIG_SMP */ 182#endif /* CONFIG_SMP */
183 183
184 .align 4 184 .align 4
185 .global bmips_reset_nmi_vec_end 185 .global bmips_reset_nmi_vec_end
186bmips_reset_nmi_vec_end: 186bmips_reset_nmi_vec_end:
187 187
188END(bmips_reset_nmi_vec) 188END(bmips_reset_nmi_vec)
@@ -206,7 +206,7 @@ LEAF(bmips_smp_int_vec)
206 eret 206 eret
207 207
208 .align 4 208 .align 4
209 .global bmips_smp_int_vec_end 209 .global bmips_smp_int_vec_end
210bmips_smp_int_vec_end: 210bmips_smp_int_vec_end:
211 211
212END(bmips_smp_int_vec) 212END(bmips_smp_int_vec)
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d735d0e58f5..83ffe950f710 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -57,7 +57,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
57 */ 57 */
58 case bcond_op: 58 case bcond_op:
59 switch (insn.i_format.rt) { 59 switch (insn.i_format.rt) {
60 case bltz_op: 60 case bltz_op:
61 case bltzl_op: 61 case bltzl_op:
62 if ((long)regs->regs[insn.i_format.rs] < 0) { 62 if ((long)regs->regs[insn.i_format.rs] < 0) {
63 epc = epc + 4 + (insn.i_format.simmediate << 2); 63 epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -197,8 +197,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
197 bit += (bit != 0); 197 bit += (bit != 0);
198 bit += 23; 198 bit += 23;
199 switch (insn.i_format.rt & 3) { 199 switch (insn.i_format.rt & 3) {
200 case 0: /* bc1f */ 200 case 0: /* bc1f */
201 case 2: /* bc1fl */ 201 case 2: /* bc1fl */
202 if (~fcr31 & (1 << bit)) { 202 if (~fcr31 & (1 << bit)) {
203 epc = epc + 4 + (insn.i_format.simmediate << 2); 203 epc = epc + 4 + (insn.i_format.simmediate << 2);
204 if (insn.i_format.rt == 2) 204 if (insn.i_format.rt == 2)
@@ -208,8 +208,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
208 regs->cp0_epc = epc; 208 regs->cp0_epc = epc;
209 break; 209 break;
210 210
211 case 1: /* bc1t */ 211 case 1: /* bc1t */
212 case 3: /* bc1tl */ 212 case 3: /* bc1tl */
213 if (fcr31 & (1 << bit)) { 213 if (fcr31 & (1 << bit)) {
214 epc = epc + 4 + (insn.i_format.simmediate << 2); 214 epc = epc + 4 + (insn.i_format.simmediate << 2);
215 if (insn.i_format.rt == 3) 215 if (insn.i_format.rt == 3)
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 69bbfae183bc..15f618b40cf6 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -41,7 +41,7 @@
41 * the rest of the system 41 * the rest of the system
42 */ 42 */
43static void sibyte_set_mode(enum clock_event_mode mode, 43static void sibyte_set_mode(enum clock_event_mode mode,
44 struct clock_event_device *evt) 44 struct clock_event_device *evt)
45{ 45{
46 unsigned int cpu = smp_processor_id(); 46 unsigned int cpu = smp_processor_id();
47 void __iomem *cfg, *init; 47 void __iomem *cfg, *init;
@@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void)
144 144
145 bcm1480_unmask_irq(cpu, irq); 145 bcm1480_unmask_irq(cpu, irq);
146 146
147 action->handler = sibyte_counter_handler; 147 action->handler = sibyte_counter_handler;
148 action->flags = IRQF_PERCPU | IRQF_TIMER; 148 action->flags = IRQF_PERCPU | IRQF_TIMER;
149 action->name = name; 149 action->name = name;
150 action->dev_id = cd; 150 action->dev_id = cd;
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index ed648cb5a69f..ff1f01b72270 100644
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DS1287 clockevent driver 2 * DS1287 clockevent driver
3 * 3 *
4 * Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -89,7 +89,7 @@ static void ds1287_event_handler(struct clock_event_device *dev)
89static struct clock_event_device ds1287_clockevent = { 89static struct clock_event_device ds1287_clockevent = {
90 .name = "ds1287", 90 .name = "ds1287",
91 .features = CLOCK_EVT_FEAT_PERIODIC, 91 .features = CLOCK_EVT_FEAT_PERIODIC,
92 .set_next_event = ds1287_set_next_event, 92 .set_next_event = ds1287_set_next_event,
93 .set_mode = ds1287_set_mode, 93 .set_mode = ds1287_set_mode,
94 .event_handler = ds1287_event_handler, 94 .event_handler = ds1287_event_handler,
95}; 95};
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 831b47585b7c..f069460751ab 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GT641xx clockevent routines. 2 * GT641xx clockevent routines.
3 * 3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -98,7 +98,7 @@ static struct clock_event_device gt641xx_timer0_clockevent = {
98 .name = "gt641xx-timer0", 98 .name = "gt641xx-timer0",
99 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 99 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
100 .irq = GT641XX_TIMER0_IRQ, 100 .irq = GT641XX_TIMER0_IRQ,
101 .set_next_event = gt641xx_timer0_set_next_event, 101 .set_next_event = gt641xx_timer0_set_next_event,
102 .set_mode = gt641xx_timer0_set_mode, 102 .set_mode = gt641xx_timer0_set_mode,
103 .event_handler = gt641xx_timer0_event_handler, 103 .event_handler = gt641xx_timer0_event_handler,
104}; 104};
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 75323925e537..07b847d77f5d 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -25,7 +25,7 @@
25#ifndef CONFIG_MIPS_MT_SMTC 25#ifndef CONFIG_MIPS_MT_SMTC
26 26
27static int mips_next_event(unsigned long delta, 27static int mips_next_event(unsigned long delta,
28 struct clock_event_device *evt) 28 struct clock_event_device *evt)
29{ 29{
30 unsigned int cnt; 30 unsigned int cnt;
31 int res; 31 int res;
@@ -66,7 +66,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
66 goto out; 66 goto out;
67 67
68 /* 68 /*
69 * The same applies to performance counter interrupts. But with the 69 * The same applies to performance counter interrupts. But with the
70 * above we now know that the reason we got here must be a timer 70 * above we now know that the reason we got here must be a timer
71 * interrupt. Being the paranoiacs we are we check anyway. 71 * interrupt. Being the paranoiacs we are we check anyway.
72 */ 72 */
@@ -119,7 +119,7 @@ int c0_compare_int_usable(void)
119 unsigned int cnt; 119 unsigned int cnt;
120 120
121 /* 121 /*
122 * IP7 already pending? Try to clear it by acking the timer. 122 * IP7 already pending? Try to clear it by acking the timer.
123 */ 123 */
124 if (c0_compare_int_pending()) { 124 if (c0_compare_int_pending()) {
125 cnt = read_c0_count(); 125 cnt = read_c0_count();
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index e73439fd6850..200f2778bf36 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -39,7 +39,7 @@
39 * the rest of the system 39 * the rest of the system
40 */ 40 */
41static void sibyte_set_mode(enum clock_event_mode mode, 41static void sibyte_set_mode(enum clock_event_mode mode,
42 struct clock_event_device *evt) 42 struct clock_event_device *evt)
43{ 43{
44 unsigned int cpu = smp_processor_id(); 44 unsigned int cpu = smp_processor_id();
45 void __iomem *cfg, *init; 45 void __iomem *cfg, *init;
@@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void)
143 143
144 sb1250_unmask_irq(cpu, irq); 144 sb1250_unmask_irq(cpu, irq);
145 145
146 action->handler = sibyte_counter_handler; 146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_PERCPU | IRQF_TIMER; 147 action->flags = IRQF_PERCPU | IRQF_TIMER;
148 action->name = name; 148 action->name = name;
149 action->dev_id = cd; 149 action->dev_id = cd;
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index 2e72d30b2f05..9de5ed7ef1a3 100644
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -49,7 +49,7 @@ static int smtc_nextinvpe[NR_CPUS];
49 49
50/* 50/*
51 * Timestamps stored are absolute values to be programmed 51 * Timestamps stored are absolute values to be programmed
52 * into Count register. Valid timestamps will never be zero. 52 * into Count register. Valid timestamps will never be zero.
53 * If a Zero Count value is actually calculated, it is converted 53 * If a Zero Count value is actually calculated, it is converted
54 * to be a 1, which will introduce 1 or two CPU cycles of error 54 * to be a 1, which will introduce 1 or two CPU cycles of error
55 * roughly once every four billion events, which at 1000 HZ means 55 * roughly once every four billion events, which at 1000 HZ means
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index e5c30b1d0860..2ae08462e46e 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Based on linux/arch/mips/kernel/cevt-r4k.c, 6 * Based on linux/arch/mips/kernel/cevt-r4k.c,
7 * linux/arch/mips/jmr3927/rbhma3100/setup.c 7 * linux/arch/mips/jmr3927/rbhma3100/setup.c
8 * 8 *
9 * Copyright 2001 MontaVista Software Inc. 9 * Copyright 2001 MontaVista Software Inc.
10 * Copyright (C) 2000-2001 Toshiba Corporation 10 * Copyright (C) 2000-2001 Toshiba Corporation
@@ -129,7 +129,7 @@ static struct txx9_clock_event_device txx9_clock_event_device = {
129 CLOCK_EVT_FEAT_ONESHOT, 129 CLOCK_EVT_FEAT_ONESHOT,
130 .rating = 200, 130 .rating = 200,
131 .set_mode = txx9tmr_set_mode, 131 .set_mode = txx9tmr_set_mode,
132 .set_next_event = txx9tmr_set_next_event, 132 .set_next_event = txx9tmr_set_next_event,
133 }, 133 },
134}; 134};
135 135
@@ -139,7 +139,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
139 struct clock_event_device *cd = &txx9_cd->cd; 139 struct clock_event_device *cd = &txx9_cd->cd;
140 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; 140 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
141 141
142 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */ 142 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
143 cd->event_handler(cd); 143 cd->event_handler(cd);
144 return IRQ_HANDLED; 144 return IRQ_HANDLED;
145} 145}
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index d6a18644365a..de3c25ffd9f9 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -84,9 +84,9 @@ static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
84 ".set noreorder\n\t" 84 ".set noreorder\n\t"
85 ".set nomacro\n\t" 85 ".set nomacro\n\t"
86 "mult %2, %3\n\t" 86 "mult %2, %3\n\t"
87 "dsll32 %0, %4, %5\n\t" 87 "dsll32 %0, %4, %5\n\t"
88 "mflo $0\n\t" 88 "mflo $0\n\t"
89 "dsll32 %1, %4, %5\n\t" 89 "dsll32 %1, %4, %5\n\t"
90 "nop\n\t" 90 "nop\n\t"
91 ".set pop" 91 ".set pop"
92 : "=&r" (lv1), "=r" (lw) 92 : "=&r" (lv1), "=r" (lw)
@@ -239,7 +239,7 @@ static inline void check_daddi(void)
239 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); 239 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
240} 240}
241 241
242int daddiu_bug = -1; 242int daddiu_bug = -1;
243 243
244static inline void check_daddiu(void) 244static inline void check_daddiu(void)
245{ 245{
@@ -273,7 +273,7 @@ static inline void check_daddiu(void)
273#ifdef HAVE_AS_SET_DADDI 273#ifdef HAVE_AS_SET_DADDI
274 ".set daddi\n\t" 274 ".set daddi\n\t"
275#endif 275#endif
276 "daddiu %0, %2, %4\n\t" 276 "daddiu %0, %2, %4\n\t"
277 "addiu %1, $0, %4\n\t" 277 "addiu %1, $0, %4\n\t"
278 "daddu %1, %2\n\t" 278 "daddu %1, %2\n\t"
279 ".set pop" 279 ".set pop"
@@ -292,7 +292,7 @@ static inline void check_daddiu(void)
292 asm volatile( 292 asm volatile(
293 "addiu %2, $0, %3\n\t" 293 "addiu %2, $0, %3\n\t"
294 "dsrl %2, %2, 1\n\t" 294 "dsrl %2, %2, 1\n\t"
295 "daddiu %0, %2, %4\n\t" 295 "daddiu %0, %2, %4\n\t"
296 "addiu %1, $0, %4\n\t" 296 "addiu %1, $0, %4\n\t"
297 "daddu %1, %2" 297 "daddu %1, %2"
298 : "=&r" (v), "=&r" (w), "=&r" (tmp) 298 : "=&r" (v), "=&r" (w), "=&r" (tmp)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cce3782c96c9..760139ee7a99 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -4,7 +4,7 @@
4 * Copyright (C) xxxx the Anonymous 4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle 5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
@@ -69,12 +69,12 @@ void r4k_wait_irqoff(void)
69 " wait \n" 69 " wait \n"
70 " .set pop \n"); 70 " .set pop \n");
71 local_irq_enable(); 71 local_irq_enable();
72 __asm__(" .globl __pastwait \n" 72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n"); 73 "__pastwait: \n");
74} 74}
75 75
76/* 76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not 77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed. 78 * have any pending stores when the WAIT instruction is executed.
79 */ 79 */
80static void rm7k_wait_irqoff(void) 80static void rm7k_wait_irqoff(void)
@@ -469,7 +469,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
469 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 469 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
470 470
471 ok = decode_config0(c); /* Read Config registers. */ 471 ok = decode_config0(c); /* Read Config registers. */
472 BUG_ON(!ok); /* Arch spec violation! */ 472 BUG_ON(!ok); /* Arch spec violation! */
473 if (ok) 473 if (ok)
474 ok = decode_config1(c); 474 ok = decode_config1(c);
475 if (ok) 475 if (ok)
@@ -710,12 +710,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
710 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 710 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
711 MIPS_CPU_LLSC; 711 MIPS_CPU_LLSC;
712 /* 712 /*
713 * Undocumented RM7000: Bit 29 in the info register of 713 * Undocumented RM7000: Bit 29 in the info register of
714 * the RM7000 v2.0 indicates if the TLB has 48 or 64 714 * the RM7000 v2.0 indicates if the TLB has 48 or 64
715 * entries. 715 * entries.
716 * 716 *
717 * 29 1 => 64 entry JTLB 717 * 29 1 => 64 entry JTLB
718 * 0 => 48 entry JTLB 718 * 0 => 48 entry JTLB
719 */ 719 */
720 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 720 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
721 break; 721 break;
@@ -729,8 +729,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
729 * Bit 29 in the info register of the RM9000 729 * Bit 29 in the info register of the RM9000
730 * indicates if the TLB has 48 or 64 entries. 730 * indicates if the TLB has 48 or 64 entries.
731 * 731 *
732 * 29 1 => 64 entry JTLB 732 * 29 1 => 64 entry JTLB
733 * 0 => 48 entry JTLB 733 * 0 => 48 entry JTLB
734 */ 734 */
735 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 735 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
736 break; 736 break;
@@ -1053,12 +1053,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1053 return; 1053 return;
1054 } 1054 }
1055 1055
1056 c->options = (MIPS_CPU_TLB | 1056 c->options = (MIPS_CPU_TLB |
1057 MIPS_CPU_4KEX | 1057 MIPS_CPU_4KEX |
1058 MIPS_CPU_COUNTER | 1058 MIPS_CPU_COUNTER |
1059 MIPS_CPU_DIVEC | 1059 MIPS_CPU_DIVEC |
1060 MIPS_CPU_WATCH | 1060 MIPS_CPU_WATCH |
1061 MIPS_CPU_EJTAG | 1061 MIPS_CPU_EJTAG |
1062 MIPS_CPU_LLSC); 1062 MIPS_CPU_LLSC);
1063 1063
1064 switch (c->processor_id & 0xff00) { 1064 switch (c->processor_id & 0xff00) {
@@ -1129,7 +1129,7 @@ __cpuinit void cpu_probe(void)
1129 struct cpuinfo_mips *c = &current_cpu_data; 1129 struct cpuinfo_mips *c = &current_cpu_data;
1130 unsigned int cpu = smp_processor_id(); 1130 unsigned int cpu = smp_processor_id();
1131 1131
1132 c->processor_id = PRID_IMP_UNKNOWN; 1132 c->processor_id = PRID_IMP_UNKNOWN;
1133 c->fpu_id = FPIR_IMP_NONE; 1133 c->fpu_id = FPIR_IMP_NONE;
1134 c->cputype = CPU_UNKNOWN; 1134 c->cputype = CPU_UNKNOWN;
1135 1135
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
index e7c98e2b78b6..bb51d3193ad4 100644
--- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -195,8 +195,8 @@ static void loongson2_cpu_wait(void)
195 195
196 spin_lock_irqsave(&loongson2_wait_lock, flags); 196 spin_lock_irqsave(&loongson2_wait_lock, flags);
197 cpu_freq = LOONGSON_CHIPCFG0; 197 cpu_freq = LOONGSON_CHIPCFG0;
198 LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */ 198 LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
199 LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */ 199 LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
200 spin_unlock_irqrestore(&loongson2_wait_lock, flags); 200 spin_unlock_irqrestore(&loongson2_wait_lock, flags);
201} 201}
202 202
diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
index 0f53c39324bb..93aa302948d7 100644
--- a/arch/mips/kernel/crash.c
+++ b/arch/mips/kernel/crash.c
@@ -59,7 +59,7 @@ static void crash_kexec_prepare_cpus(void)
59 59
60#else /* !defined(CONFIG_SMP) */ 60#else /* !defined(CONFIG_SMP) */
61static void crash_kexec_prepare_cpus(void) {} 61static void crash_kexec_prepare_cpus(void) {}
62#endif /* !defined(CONFIG_SMP) */ 62#endif /* !defined(CONFIG_SMP) */
63 63
64void default_machine_crash_shutdown(struct pt_regs *regs) 64void default_machine_crash_shutdown(struct pt_regs *regs)
65{ 65{
diff --git a/arch/mips/kernel/csrc-bcm1480.c b/arch/mips/kernel/csrc-bcm1480.c
index f96f99c794a3..468f3eba4132 100644
--- a/arch/mips/kernel/csrc-bcm1480.c
+++ b/arch/mips/kernel/csrc-bcm1480.c
@@ -35,7 +35,7 @@ static cycle_t bcm1480_hpt_read(struct clocksource *cs)
35 35
36struct clocksource bcm1480_clocksource = { 36struct clocksource bcm1480_clocksource = {
37 .name = "zbbus-cycles", 37 .name = "zbbus-cycles",
38 .rating = 200, 38 .rating = 200,
39 .read = bcm1480_hpt_read, 39 .read = bcm1480_hpt_read,
40 .mask = CLOCKSOURCE_MASK(64), 40 .mask = CLOCKSOURCE_MASK(64),
41 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 41 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 46bd7fa98d6c..0654bff9b69c 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DEC I/O ASIC's counter clocksource 2 * DEC I/O ASIC's counter clocksource
3 * 3 *
4 * Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
index 2e7c5232da8d..abd99ea911ae 100644
--- a/arch/mips/kernel/csrc-powertv.c
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -45,7 +45,7 @@ unsigned int __init mips_get_pll_freq(void)
45 m = PLL_GET_M(pll_reg); 45 m = PLL_GET_M(pll_reg);
46 n = PLL_GET_N(pll_reg); 46 n = PLL_GET_N(pll_reg);
47 p = PLL_GET_P(pll_reg); 47 p = PLL_GET_P(pll_reg);
48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); 48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49 49
50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ 50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51 fout = ((2 * n * fin) / (m * (0x01 << p))); 51 fout = ((2 * n * fin) / (m * (0x01 << p)));
@@ -83,8 +83,8 @@ static void __init powertv_c0_hpt_clocksource_init(void)
83 83
84/** 84/**
85 * struct tim_c - free running counter 85 * struct tim_c - free running counter
86 * @hi: High 16 bits of the counter 86 * @hi: High 16 bits of the counter
87 * @lo: Low 32 bits of the counter 87 * @lo: Low 32 bits of the counter
88 * 88 *
89 * Lays out the structure of the free running counter in memory. This counter 89 * Lays out the structure of the free running counter in memory. This counter
90 * increments at a rate of 27 MHz/8 on all platforms. 90 * increments at a rate of 27 MHz/8 on all platforms.
diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index e9606d907685..6ecb77d82063 100644
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -44,7 +44,7 @@ static cycle_t sb1250_hpt_read(struct clocksource *cs)
44 44
45struct clocksource bcm1250_clocksource = { 45struct clocksource bcm1250_clocksource = {
46 .name = "bcm1250-counter-3", 46 .name = "bcm1250-counter-3",
47 .rating = 200, 47 .rating = 200,
48 .read = sb1250_hpt_read, 48 .read = sb1250_hpt_read,
49 .mask = CLOCKSOURCE_MASK(23), 49 .mask = CLOCKSOURCE_MASK(23),
50 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 83fa1460e294..cf5509f13dd5 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -125,21 +125,21 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
125 * 125 *
126 * 2.1 For KBUILD_MCOUNT_RA_ADDRESS and CONFIG_32BIT 126 * 2.1 For KBUILD_MCOUNT_RA_ADDRESS and CONFIG_32BIT
127 * 127 *
128 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000005) 128 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000005)
129 * addiu v1, v1, low_16bit_of_mcount 129 * addiu v1, v1, low_16bit_of_mcount
130 * move at, ra 130 * move at, ra
131 * move $12, ra_address 131 * move $12, ra_address
132 * jalr v1 132 * jalr v1
133 * sub sp, sp, 8 133 * sub sp, sp, 8
134 * 1: offset = 5 instructions 134 * 1: offset = 5 instructions
135 * 2.2 For the Other situations 135 * 2.2 For the Other situations
136 * 136 *
137 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000004) 137 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
138 * addiu v1, v1, low_16bit_of_mcount 138 * addiu v1, v1, low_16bit_of_mcount
139 * move at, ra 139 * move at, ra
140 * jalr v1 140 * jalr v1
141 * nop | move $12, ra_address | sub sp, sp, 8 141 * nop | move $12, ra_address | sub sp, sp, 8
142 * 1: offset = 4 instructions 142 * 1: offset = 4 instructions
143 */ 143 */
144 144
145#define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS) 145#define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
@@ -228,8 +228,8 @@ int ftrace_disable_ftrace_graph_caller(void)
228 228
229#ifndef KBUILD_MCOUNT_RA_ADDRESS 229#ifndef KBUILD_MCOUNT_RA_ADDRESS
230 230
231#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */ 231#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */
232#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ 232#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
233#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ 233#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
234 234
235unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long 235unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 8a0096d62812..ecb347ce1b3d 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -160,7 +160,7 @@ LEAF(r4k_wait)
160 .set pop 160 .set pop
161 .endm 161 .endm
162 162
163 .align 5 163 .align 5
164BUILD_ROLLBACK_PROLOGUE handle_int 164BUILD_ROLLBACK_PROLOGUE handle_int
165NESTED(handle_int, PT_SIZE, sp) 165NESTED(handle_int, PT_SIZE, sp)
166#ifdef CONFIG_TRACE_IRQFLAGS 166#ifdef CONFIG_TRACE_IRQFLAGS
@@ -362,7 +362,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
362 .set push 362 .set push
363 .set noat 363 .set noat
364 SAVE_ALL 364 SAVE_ALL
365 move a0, sp 365 move a0, sp
366 jal nmi_exception_handler 366 jal nmi_exception_handler
367 RESTORE_ALL 367 RESTORE_ALL
368 .set mips3 368 .set mips3
@@ -409,7 +409,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
409 string escapes and emits bogus warnings if it believes to 409 string escapes and emits bogus warnings if it believes to
410 recognize an unknown escape code. So make the arguments 410 recognize an unknown escape code. So make the arguments
411 start with an n and gas will believe \n is ok ... */ 411 start with an n and gas will believe \n is ok ... */
412 .macro __BUILD_verbose nexception 412 .macro __BUILD_verbose nexception
413 LONG_L a1, PT_EPC(sp) 413 LONG_L a1, PT_EPC(sp)
414#ifdef CONFIG_32BIT 414#ifdef CONFIG_32BIT
415 PRINT("Got \nexception at %08lx\012") 415 PRINT("Got \nexception at %08lx\012")
@@ -442,7 +442,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
442 .endm 442 .endm
443 443
444 .macro BUILD_HANDLER exception handler clear verbose 444 .macro BUILD_HANDLER exception handler clear verbose
445 __BUILD_HANDLER \exception \handler \clear \verbose _int 445 __BUILD_HANDLER \exception \handler \clear \verbose _int
446 .endm 446 .endm
447 447
448 BUILD_HANDLER adel ade ade silent /* #4 */ 448 BUILD_HANDLER adel ade ade silent /* #4 */
@@ -456,7 +456,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
456 BUILD_HANDLER tr tr sti silent /* #13 */ 456 BUILD_HANDLER tr tr sti silent /* #13 */
457 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 457 BUILD_HANDLER fpe fpe fpe silent /* #15 */
458 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 458 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
459#ifdef CONFIG_HARDWARE_WATCHPOINTS 459#ifdef CONFIG_HARDWARE_WATCHPOINTS
460 /* 460 /*
461 * For watch, interrupts will be enabled after the watch 461 * For watch, interrupts will be enabled after the watch
462 * registers are read. 462 * registers are read.
@@ -482,8 +482,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
482 MFC0 k1, CP0_ENTRYHI 482 MFC0 k1, CP0_ENTRYHI
483 andi k1, 0xff /* ASID_MASK */ 483 andi k1, 0xff /* ASID_MASK */
484 MFC0 k0, CP0_EPC 484 MFC0 k0, CP0_EPC
485 PTR_SRL k0, _PAGE_SHIFT + 1 485 PTR_SRL k0, _PAGE_SHIFT + 1
486 PTR_SLL k0, _PAGE_SHIFT + 1 486 PTR_SLL k0, _PAGE_SHIFT + 1
487 or k1, k0 487 or k1, k0
488 MTC0 k1, CP0_ENTRYHI 488 MTC0 k1, CP0_ENTRYHI
489 mtc0_tlbw_hazard 489 mtc0_tlbw_hazard
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index fcf97312f328..c61cdaed2b1d 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -133,7 +133,7 @@ EXPORT(_stext)
133#ifdef CONFIG_BOOT_RAW 133#ifdef CONFIG_BOOT_RAW
134 /* 134 /*
135 * Give us a fighting chance of running if execution beings at the 135 * Give us a fighting chance of running if execution beings at the
136 * kernel load address. This is needed because this platform does 136 * kernel load address. This is needed because this platform does
137 * not have a ELF loader yet. 137 * not have a ELF loader yet.
138 */ 138 */
139FEXPORT(__kernel_entry) 139FEXPORT(__kernel_entry)
@@ -201,7 +201,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
201 201
202#ifdef CONFIG_SMP 202#ifdef CONFIG_SMP
203/* 203/*
204 * SMP slave cpus entry point. Board specific code for bootstrap calls this 204 * SMP slave cpus entry point. Board specific code for bootstrap calls this
205 * function after setting up the stack and gp registers. 205 * function after setting up the stack and gp registers.
206 */ 206 */
207NESTED(smp_bootstrap, 16, sp) 207NESTED(smp_bootstrap, 16, sp)
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 32b397b646ee..2b91fe80c436 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -178,7 +178,7 @@ handle_real_irq:
178 } else { 178 } else {
179 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 179 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
180 outb(cached_master_mask, PIC_MASTER_IMR); 180 outb(cached_master_mask, PIC_MASTER_IMR);
181 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ 181 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
182 } 182 }
183 smtc_im_ack_irq(irq); 183 smtc_im_ack_irq(irq);
184 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 184 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 883fc6cead36..44a1f792e399 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GT641xx IRQ routines. 2 * GT641xx IRQ routines.
3 * 3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -25,7 +25,7 @@
25 25
26#include <asm/gt64120.h> 26#include <asm/gt64120.h>
27 27
28#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE)) 28#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
29 29
30static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); 30static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
31 31
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 14ac52c5ae86..fab40f7d2e03 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * This program is free software; you can redistribute it and/or modify it 2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the 3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your 4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version. 5 * option) any later version.
6 * 6 *
@@ -86,7 +86,7 @@ static void edge_mask_and_ack_msc_irq(struct irq_data *d)
86 */ 86 */
87void ll_msc_irq(void) 87void ll_msc_irq(void)
88{ 88{
89 unsigned int irq; 89 unsigned int irq;
90 90
91 /* read the interrupt vector register */ 91 /* read the interrupt vector register */
92 MSCIC_READ(MSC01_IC_VEC, irq); 92 MSCIC_READ(MSC01_IC_VEC, irq);
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index b0662cf97ea8..26f4e4c9db1a 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2003 Ralf Baechle 2 * Copyright (C) 2003 Ralf Baechle
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your 6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version. 7 * option) any later version.
8 * 8 *
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a5aa43d07c8e..d1fea7a054be 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -48,7 +48,7 @@ again:
48} 48}
49 49
50/* 50/*
51 * Allocate the 16 legacy interrupts for i8259 devices. This happens early 51 * Allocate the 16 legacy interrupts for i8259 devices. This happens early
52 * in the kernel initialization so treating allocation failure as BUG() is 52 * in the kernel initialization so treating allocation failure as BUG() is
53 * ok. 53 * ok.
54 */ 54 */
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 972263bcf403..0207a44917bf 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -3,13 +3,13 @@
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * 4 *
5 * Copyright (C) 2001 Ralf Baechle 5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com> 7 * Author: Maciej W. Rozycki <macro@mips.com>
8 * 8 *
9 * This file define the irq handler for MIPS CPU interrupts. 9 * This file define the irq handler for MIPS CPU interrupts.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your 13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index b0c55b50218e..ab00e490482f 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -1,12 +1,12 @@
1/* 1/*
2 * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c, 2 * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
3 * linux/arch/mips/tx4927/common/tx4927_irq.c, 3 * linux/arch/mips/tx4927/common/tx4927_irq.c,
4 * linux/arch/mips/tx4938/common/irq.c 4 * linux/arch/mips/tx4938/common/irq.c
5 * 5 *
6 * Copyright 2001, 2003-2005 MontaVista Software Inc. 6 * Copyright 2001, 2003-2005 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com 8 * ahennessy@mvista.com
9 * source@mvista.com 9 * source@mvista.com
10 * Copyright (C) 2000-2001 Toshiba Corporation 10 * Copyright (C) 2000-2001 Toshiba Corporation
11 * 11 *
12 * This file is subject to the terms and conditions of the GNU General Public 12 * This file is subject to the terms and conditions of the GNU General Public
@@ -122,7 +122,7 @@ static int txx9_irq_set_type(struct irq_data *d, unsigned int flow_type)
122 switch (flow_type & IRQF_TRIGGER_MASK) { 122 switch (flow_type & IRQF_TRIGGER_MASK) {
123 case IRQF_TRIGGER_RISING: mode = TXx9_IRCR_UP; break; 123 case IRQF_TRIGGER_RISING: mode = TXx9_IRCR_UP; break;
124 case IRQF_TRIGGER_FALLING: mode = TXx9_IRCR_DOWN; break; 124 case IRQF_TRIGGER_FALLING: mode = TXx9_IRCR_DOWN; break;
125 case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH; break; 125 case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH; break;
126 case IRQF_TRIGGER_LOW: mode = TXx9_IRCR_LOW; break; 126 case IRQF_TRIGGER_LOW: mode = TXx9_IRCR_LOW; break;
127 default: 127 default:
128 return -EINVAL; 128 return -EINVAL;
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 23817a6e32b6..fcaac2f132f0 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -40,7 +40,7 @@ static struct hard_trap_info {
40 { 6, SIGBUS }, /* instruction bus error */ 40 { 6, SIGBUS }, /* instruction bus error */
41 { 7, SIGBUS }, /* data bus error */ 41 { 7, SIGBUS }, /* data bus error */
42 { 9, SIGTRAP }, /* break */ 42 { 9, SIGTRAP }, /* break */
43/* { 11, SIGILL }, */ /* CPU unusable */ 43/* { 11, SIGILL }, */ /* CPU unusable */
44 { 12, SIGFPE }, /* overflow */ 44 { 12, SIGFPE }, /* overflow */
45 { 13, SIGTRAP }, /* trap */ 45 { 13, SIGTRAP }, /* trap */
46 { 14, SIGSEGV }, /* virtual instruction cache coherency */ 46 { 14, SIGSEGV }, /* virtual instruction cache coherency */
@@ -321,7 +321,7 @@ int kgdb_ll_trap(int cmd, const char *str,
321 .regs = regs, 321 .regs = regs,
322 .str = str, 322 .str = str,
323 .err = err, 323 .err = err,
324 .trapnr = trap, 324 .trapnr = trap,
325 .signr = sig, 325 .signr = sig,
326 326
327 }; 327 };
@@ -371,7 +371,7 @@ int kgdb_arch_init(void)
371 union mips_instruction insn = { 371 union mips_instruction insn = {
372 .r_format = { 372 .r_format = {
373 .opcode = spec_op, 373 .opcode = spec_op,
374 .func = break_op, 374 .func = break_op,
375 } 375 }
376 }; 376 };
377 memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE); 377 memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE);
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index 158467da9bc1..a14be5fa5ec8 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -307,7 +307,7 @@ static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
307/* 307/*
308 * Called after single-stepping. p->addr is the address of the 308 * Called after single-stepping. p->addr is the address of the
309 * instruction whose first byte has been replaced by the "break 0" 309 * instruction whose first byte has been replaced by the "break 0"
310 * instruction. To avoid the SMP problems that can occur when we 310 * instruction. To avoid the SMP problems that can occur when we
311 * temporarily put back the original opcode to single-step, we 311 * temporarily put back the original opcode to single-step, we
312 * single-stepped a copy of the instruction. The address of this 312 * single-stepped a copy of the instruction. The address of this
313 * copy is p->ainsn.insn. 313 * copy is p->ainsn.insn.
@@ -535,7 +535,7 @@ void jprobe_return_end(void);
535 535
536void __kprobes jprobe_return(void) 536void __kprobes jprobe_return(void)
537{ 537{
538 /* Assembler quirk necessitates this '0,code' business. */ 538 /* Assembler quirk necessitates this '0,code' business. */
539 asm volatile( 539 asm volatile(
540 "break 0,%0\n\t" 540 "break 0,%0\n\t"
541 ".globl jprobe_return_end\n" 541 ".globl jprobe_return_end\n"
@@ -614,9 +614,9 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
614 * We can handle this because: 614 * We can handle this because:
615 * - instances are always inserted at the head of the list 615 * - instances are always inserted at the head of the list
616 * - when multiple return probes are registered for the same 616 * - when multiple return probes are registered for the same
617 * function, the first instance's ret_addr will point to the 617 * function, the first instance's ret_addr will point to the
618 * real return address, and all the rest will point to 618 * real return address, and all the rest will point to
619 * kretprobe_trampoline 619 * kretprobe_trampoline
620 */ 620 */
621 hlist_for_each_entry_safe(ri, node, tmp, head, hlist) { 621 hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
622 if (ri->task != current) 622 if (ri->task != current)
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 7adab86c632c..16bf4a5d3d1a 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -76,7 +76,7 @@ out:
76 return error; 76 return error;
77} 77}
78 78
79#define RLIM_INFINITY32 0x7fffffff 79#define RLIM_INFINITY32 0x7fffffff
80#define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x) 80#define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x)
81 81
82struct rlimit32 { 82struct rlimit32 {
@@ -105,7 +105,7 @@ SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
105 105
106/* From the Single Unix Spec: pread & pwrite act like lseek to pos + op + 106/* From the Single Unix Spec: pread & pwrite act like lseek to pos + op +
107 lseek back to original location. They fail just like lseek does on 107 lseek back to original location. They fail just like lseek does on
108 non-seekable files. */ 108 non-seekable files. */
109 109
110SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count, 110SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count,
111 unsigned long, unused, unsigned long, a4, unsigned long, a5) 111 unsigned long, unused, unsigned long, a4, unsigned long, a5)
@@ -263,7 +263,7 @@ SYSCALL_DEFINE4(32_sendfile, long, out_fd, long, in_fd,
263} 263}
264 264
265asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3, 265asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3,
266 size_t count) 266 size_t count)
267{ 267{
268 return sys_readahead(fd, merge_64(a2, a3), count); 268 return sys_readahead(fd, merge_64(a2, a3), count);
269} 269}
@@ -292,7 +292,7 @@ asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
292 unsigned offset_a3, unsigned len_a4, unsigned len_a5) 292 unsigned offset_a3, unsigned len_a4, unsigned len_a5)
293{ 293{
294 return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3), 294 return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
295 merge_64(len_a4, len_a5)); 295 merge_64(len_a4, len_a5));
296} 296}
297 297
298save_static_function(sys32_clone); 298save_static_function(sys32_clone);
@@ -313,7 +313,7 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
313 syscall() works. */ 313 syscall() works. */
314 child_tidptr = (int __user *) __dummy4; 314 child_tidptr = (int __user *) __dummy4;
315 return do_fork(clone_flags, newsp, 0, 315 return do_fork(clone_flags, newsp, 0,
316 parent_tidptr, child_tidptr); 316 parent_tidptr, child_tidptr);
317} 317}
318 318
319asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf, 319asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
@@ -323,7 +323,7 @@ asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
323} 323}
324 324
325SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags, 325SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
326 u64, a3, u64, a4, int, dfd, const char __user *, pathname) 326 u64, a3, u64, a4, int, dfd, const char __user *, pathname)
327{ 327{
328 return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4), 328 return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
329 dfd, pathname); 329 dfd, pathname);
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index df1e3e455f9a..6e58e97fcd39 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -17,9 +17,9 @@
17 17
18extern void *__bzero(void *__s, size_t __count); 18extern void *__bzero(void *__s, size_t __count);
19extern long __strncpy_from_user_nocheck_asm(char *__to, 19extern long __strncpy_from_user_nocheck_asm(char *__to,
20 const char *__from, long __len); 20 const char *__from, long __len);
21extern long __strncpy_from_user_asm(char *__to, const char *__from, 21extern long __strncpy_from_user_asm(char *__to, const char *__from,
22 long __len); 22 long __len);
23extern long __strlen_user_nocheck_asm(const char *s); 23extern long __strlen_user_nocheck_asm(const char *s);
24extern long __strlen_user_asm(const char *s); 24extern long __strlen_user_asm(const char *s);
25extern long __strnlen_user_nocheck_asm(const char *s); 25extern long __strnlen_user_nocheck_asm(const char *s);
diff --git a/arch/mips/kernel/module-rela.c b/arch/mips/kernel/module-rela.c
index 61d60028b888..2b70723071c3 100644
--- a/arch/mips/kernel/module-rela.c
+++ b/arch/mips/kernel/module-rela.c
@@ -55,7 +55,7 @@ static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
55static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v) 55static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
56{ 56{
57 *location = (*location & 0xffff0000) | 57 *location = (*location & 0xffff0000) |
58 ((((long long) v + 0x8000LL) >> 16) & 0xffff); 58 ((((long long) v + 0x8000LL) >> 16) & 0xffff);
59 59
60 return 0; 60 return 0;
61} 61}
@@ -78,7 +78,7 @@ static int apply_r_mips_higher_rela(struct module *me, u32 *location,
78 Elf_Addr v) 78 Elf_Addr v)
79{ 79{
80 *location = (*location & 0xffff0000) | 80 *location = (*location & 0xffff0000) |
81 ((((long long) v + 0x80008000LL) >> 32) & 0xffff); 81 ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
82 82
83 return 0; 83 return 0;
84} 84}
@@ -87,7 +87,7 @@ static int apply_r_mips_highest_rela(struct module *me, u32 *location,
87 Elf_Addr v) 87 Elf_Addr v)
88{ 88{
89 *location = (*location & 0xffff0000) | 89 *location = (*location & 0xffff0000) |
90 ((((long long) v + 0x800080008000LL) >> 48) & 0xffff); 90 ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
91 91
92 return 0; 92 return 0;
93} 93}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 07ff5812ffaf..977a623d9253 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -79,7 +79,7 @@ static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
79 } 79 }
80 80
81 *location = (*location & ~0x03ffffff) | 81 *location = (*location & ~0x03ffffff) |
82 ((*location + (v >> 2)) & 0x03ffffff); 82 ((*location + (v >> 2)) & 0x03ffffff);
83 83
84 return 0; 84 return 0;
85} 85}
@@ -122,7 +122,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
122 struct mips_hi16 *l; 122 struct mips_hi16 *l;
123 Elf_Addr val, vallo; 123 Elf_Addr val, vallo;
124 124
125 /* Sign extend the addend we extract from the lo insn. */ 125 /* Sign extend the addend we extract from the lo insn. */
126 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; 126 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
127 127
128 if (me->arch.r_mips_hi16_list != NULL) { 128 if (me->arch.r_mips_hi16_list != NULL) {
@@ -165,7 +165,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
165 } 165 }
166 166
167 /* 167 /*
168 * Ok, we're done with the HI16 relocs. Now deal with the LO16. 168 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
169 */ 169 */
170 val = v + vallo; 170 val = v + vallo;
171 insnlo = (insnlo & ~0xffff) | (val & 0xffff); 171 insnlo = (insnlo & ~0xffff) | (val & 0xffff);
@@ -230,7 +230,7 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
230 } 230 }
231 231
232 /* 232 /*
233 * Normally the hi16 list should be deallocated at this point. A 233 * Normally the hi16 list should be deallocated at this point. A
234 * malformed binary however could contain a series of R_MIPS_HI16 234 * malformed binary however could contain a series of R_MIPS_HI16
235 * relocations not followed by a R_MIPS_LO16 relocation. In that 235 * relocations not followed by a R_MIPS_LO16 relocation. In that
236 * case, free up the list and return an error. 236 * case, free up the list and return an error.
@@ -261,7 +261,7 @@ const struct exception_table_entry *search_module_dbetables(unsigned long addr)
261 spin_unlock_irqrestore(&dbe_lock, flags); 261 spin_unlock_irqrestore(&dbe_lock, flags);
262 262
263 /* Now, if we found one, we are running inside it now, hence 263 /* Now, if we found one, we are running inside it now, hence
264 we cannot unload the module, hence no refcnt needed. */ 264 we cannot unload the module, hence no refcnt needed. */
265 return e; 265 return e;
266} 266}
267 267
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 207f1341578b..0e23343eb0a9 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -30,7 +30,7 @@
30 30
31/* 31/*
32 * task_struct *resume(task_struct *prev, task_struct *next, 32 * task_struct *resume(task_struct *prev, task_struct *next,
33 * struct thread_info *next_ti, int usedfpu) 33 * struct thread_info *next_ti, int usedfpu)
34 */ 34 */
35 .align 7 35 .align 7
36 LEAF(resume) 36 LEAF(resume)
@@ -69,7 +69,7 @@
691: 691:
70#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 70#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
71 /* Check if we need to store CVMSEG state */ 71 /* Check if we need to store CVMSEG state */
72 mfc0 t0, $11,7 /* CvmMemCtl */ 72 mfc0 t0, $11,7 /* CvmMemCtl */
73 bbit0 t0, 6, 3f /* Is user access enabled? */ 73 bbit0 t0, 6, 3f /* Is user access enabled? */
74 74
75 /* Store the CVMSEG state */ 75 /* Store the CVMSEG state */
@@ -77,8 +77,8 @@
77 andi t0, 0x3f 77 andi t0, 0x3f
78 /* Multiply * (cache line size/sizeof(long)/2) */ 78 /* Multiply * (cache line size/sizeof(long)/2) */
79 sll t0, 7-LONGLOG-1 79 sll t0, 7-LONGLOG-1
80 li t1, -32768 /* Base address of CVMSEG */ 80 li t1, -32768 /* Base address of CVMSEG */
81 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ 81 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
82 synciobdma 82 synciobdma
832: 832:
84 .set noreorder 84 .set noreorder
@@ -89,13 +89,13 @@
89 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ 89 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
90 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ 90 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
91 bnez t0, 2b /* Loop until we've copied it all */ 91 bnez t0, 2b /* Loop until we've copied it all */
92 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ 92 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
93 .set reorder 93 .set reorder
94 94
95 /* Disable access to CVMSEG */ 95 /* Disable access to CVMSEG */
96 mfc0 t0, $11,7 /* CvmMemCtl */ 96 mfc0 t0, $11,7 /* CvmMemCtl */
97 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ 97 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
98 mtc0 t0, $11,7 /* CvmMemCtl */ 98 mtc0 t0, $11,7 /* CvmMemCtl */
99#endif 99#endif
1003: 1003:
101 /* 101 /*
@@ -133,7 +133,7 @@
133 133
134 dmfc0 t9, $9,7 /* CvmCtl register. */ 134 dmfc0 t9, $9,7 /* CvmCtl register. */
135 135
136 /* Save the COP2 CRC state */ 136 /* Save the COP2 CRC state */
137 dmfc2 t0, 0x0201 137 dmfc2 t0, 0x0201
138 dmfc2 t1, 0x0202 138 dmfc2 t1, 0x0202
139 dmfc2 t2, 0x0200 139 dmfc2 t2, 0x0200
@@ -149,30 +149,30 @@
149 sd t0, OCTEON_CP2_LLM_DAT(a0) 149 sd t0, OCTEON_CP2_LLM_DAT(a0)
150 sd t1, OCTEON_CP2_LLM_DAT+8(a0) 150 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
151 151
1521: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ 1521: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
153 153
154 /* Save the COP2 crypto state */ 154 /* Save the COP2 crypto state */
155 /* this part is mostly common to both pass 1 and later revisions */ 155 /* this part is mostly common to both pass 1 and later revisions */
156 dmfc2 t0, 0x0084 156 dmfc2 t0, 0x0084
157 dmfc2 t1, 0x0080 157 dmfc2 t1, 0x0080
158 dmfc2 t2, 0x0081 158 dmfc2 t2, 0x0081
159 dmfc2 t3, 0x0082 159 dmfc2 t3, 0x0082
160 sd t0, OCTEON_CP2_3DES_IV(a0) 160 sd t0, OCTEON_CP2_3DES_IV(a0)
161 dmfc2 t0, 0x0088 161 dmfc2 t0, 0x0088
162 sd t1, OCTEON_CP2_3DES_KEY(a0) 162 sd t1, OCTEON_CP2_3DES_KEY(a0)
163 dmfc2 t1, 0x0111 /* only necessary for pass 1 */ 163 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
164 sd t2, OCTEON_CP2_3DES_KEY+8(a0) 164 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
165 dmfc2 t2, 0x0102 165 dmfc2 t2, 0x0102
166 sd t3, OCTEON_CP2_3DES_KEY+16(a0) 166 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
167 dmfc2 t3, 0x0103 167 dmfc2 t3, 0x0103
168 sd t0, OCTEON_CP2_3DES_RESULT(a0) 168 sd t0, OCTEON_CP2_3DES_RESULT(a0)
169 dmfc2 t0, 0x0104 169 dmfc2 t0, 0x0104
170 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ 170 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
171 dmfc2 t1, 0x0105 171 dmfc2 t1, 0x0105
172 sd t2, OCTEON_CP2_AES_IV(a0) 172 sd t2, OCTEON_CP2_AES_IV(a0)
173 dmfc2 t2, 0x0106 173 dmfc2 t2, 0x0106
174 sd t3, OCTEON_CP2_AES_IV+8(a0) 174 sd t3, OCTEON_CP2_AES_IV+8(a0)
175 dmfc2 t3, 0x0107 175 dmfc2 t3, 0x0107
176 sd t0, OCTEON_CP2_AES_KEY(a0) 176 sd t0, OCTEON_CP2_AES_KEY(a0)
177 dmfc2 t0, 0x0110 177 dmfc2 t0, 0x0110
178 sd t1, OCTEON_CP2_AES_KEY+8(a0) 178 sd t1, OCTEON_CP2_AES_KEY+8(a0)
@@ -180,7 +180,7 @@
180 sd t2, OCTEON_CP2_AES_KEY+16(a0) 180 sd t2, OCTEON_CP2_AES_KEY+16(a0)
181 dmfc2 t2, 0x0101 181 dmfc2 t2, 0x0101
182 sd t3, OCTEON_CP2_AES_KEY+24(a0) 182 sd t3, OCTEON_CP2_AES_KEY+24(a0)
183 mfc0 t3, $15,0 /* Get the processor ID register */ 183 mfc0 t3, $15,0 /* Get the processor ID register */
184 sd t0, OCTEON_CP2_AES_KEYLEN(a0) 184 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
185 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 185 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
186 sd t1, OCTEON_CP2_AES_RESULT(a0) 186 sd t1, OCTEON_CP2_AES_RESULT(a0)
@@ -188,7 +188,7 @@
188 /* Skip to the Pass1 version of the remainder of the COP2 state */ 188 /* Skip to the Pass1 version of the remainder of the COP2 state */
189 beq t3, t0, 2f 189 beq t3, t0, 2f
190 190
191 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ 191 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
192 dmfc2 t1, 0x0240 192 dmfc2 t1, 0x0240
193 dmfc2 t2, 0x0241 193 dmfc2 t2, 0x0241
194 dmfc2 t3, 0x0242 194 dmfc2 t3, 0x0242
@@ -214,7 +214,7 @@
214 sd t2, OCTEON_CP2_HSH_DATW+72(a0) 214 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
215 dmfc2 t2, 0x024D 215 dmfc2 t2, 0x024D
216 sd t3, OCTEON_CP2_HSH_DATW+80(a0) 216 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
217 dmfc2 t3, 0x024E 217 dmfc2 t3, 0x024E
218 sd t0, OCTEON_CP2_HSH_DATW+88(a0) 218 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
219 dmfc2 t0, 0x0250 219 dmfc2 t0, 0x0250
220 sd t1, OCTEON_CP2_HSH_DATW+96(a0) 220 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
@@ -232,9 +232,9 @@
232 sd t3, OCTEON_CP2_HSH_IVW+24(a0) 232 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
233 dmfc2 t3, 0x0257 233 dmfc2 t3, 0x0257
234 sd t0, OCTEON_CP2_HSH_IVW+32(a0) 234 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
235 dmfc2 t0, 0x0258 235 dmfc2 t0, 0x0258
236 sd t1, OCTEON_CP2_HSH_IVW+40(a0) 236 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
237 dmfc2 t1, 0x0259 237 dmfc2 t1, 0x0259
238 sd t2, OCTEON_CP2_HSH_IVW+48(a0) 238 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
239 dmfc2 t2, 0x025E 239 dmfc2 t2, 0x025E
240 sd t3, OCTEON_CP2_HSH_IVW+56(a0) 240 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
@@ -247,7 +247,7 @@
247 sd t0, OCTEON_CP2_GFM_RESULT+8(a0) 247 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
248 jr ra 248 jr ra
249 249
2502: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ 2502: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
251 dmfc2 t3, 0x0040 251 dmfc2 t3, 0x0040
252 dmfc2 t0, 0x0041 252 dmfc2 t0, 0x0041
253 dmfc2 t1, 0x0042 253 dmfc2 t1, 0x0042
@@ -269,7 +269,7 @@
269 sd t3, OCTEON_CP2_HSH_IVW+8(a0) 269 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
270 sd t0, OCTEON_CP2_HSH_IVW+16(a0) 270 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
271 271
2723: /* pass 1 or CvmCtl[NOCRYPTO] set */ 2723: /* pass 1 or CvmCtl[NOCRYPTO] set */
273 jr ra 273 jr ra
274 END(octeon_cop2_save) 274 END(octeon_cop2_save)
275 275
@@ -280,19 +280,19 @@
280 .set push 280 .set push
281 .set noreorder 281 .set noreorder
282 LEAF(octeon_cop2_restore) 282 LEAF(octeon_cop2_restore)
283 /* First cache line was prefetched before the call */ 283 /* First cache line was prefetched before the call */
284 pref 4, 128(a0) 284 pref 4, 128(a0)
285 dmfc0 t9, $9,7 /* CvmCtl register. */ 285 dmfc0 t9, $9,7 /* CvmCtl register. */
286 286
287 pref 4, 256(a0) 287 pref 4, 256(a0)
288 ld t0, OCTEON_CP2_CRC_IV(a0) 288 ld t0, OCTEON_CP2_CRC_IV(a0)
289 pref 4, 384(a0) 289 pref 4, 384(a0)
290 ld t1, OCTEON_CP2_CRC_LENGTH(a0) 290 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
291 ld t2, OCTEON_CP2_CRC_POLY(a0) 291 ld t2, OCTEON_CP2_CRC_POLY(a0)
292 292
293 /* Restore the COP2 CRC state */ 293 /* Restore the COP2 CRC state */
294 dmtc2 t0, 0x0201 294 dmtc2 t0, 0x0201
295 dmtc2 t1, 0x1202 295 dmtc2 t1, 0x1202
296 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ 296 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
297 dmtc2 t2, 0x4200 297 dmtc2 t2, 0x4200
298 298
@@ -310,19 +310,19 @@
310 ld t0, OCTEON_CP2_3DES_IV(a0) 310 ld t0, OCTEON_CP2_3DES_IV(a0)
311 ld t1, OCTEON_CP2_3DES_KEY(a0) 311 ld t1, OCTEON_CP2_3DES_KEY(a0)
312 ld t2, OCTEON_CP2_3DES_KEY+8(a0) 312 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
313 dmtc2 t0, 0x0084 313 dmtc2 t0, 0x0084
314 ld t0, OCTEON_CP2_3DES_KEY+16(a0) 314 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
315 dmtc2 t1, 0x0080 315 dmtc2 t1, 0x0080
316 ld t1, OCTEON_CP2_3DES_RESULT(a0) 316 ld t1, OCTEON_CP2_3DES_RESULT(a0)
317 dmtc2 t2, 0x0081 317 dmtc2 t2, 0x0081
318 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ 318 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
319 dmtc2 t0, 0x0082 319 dmtc2 t0, 0x0082
320 ld t0, OCTEON_CP2_AES_IV(a0) 320 ld t0, OCTEON_CP2_AES_IV(a0)
321 dmtc2 t1, 0x0098 321 dmtc2 t1, 0x0098
322 ld t1, OCTEON_CP2_AES_IV+8(a0) 322 ld t1, OCTEON_CP2_AES_IV+8(a0)
323 dmtc2 t2, 0x010A /* only really needed for pass 1 */ 323 dmtc2 t2, 0x010A /* only really needed for pass 1 */
324 ld t2, OCTEON_CP2_AES_KEY(a0) 324 ld t2, OCTEON_CP2_AES_KEY(a0)
325 dmtc2 t0, 0x0102 325 dmtc2 t0, 0x0102
326 ld t0, OCTEON_CP2_AES_KEY+8(a0) 326 ld t0, OCTEON_CP2_AES_KEY+8(a0)
327 dmtc2 t1, 0x0103 327 dmtc2 t1, 0x0103
328 ld t1, OCTEON_CP2_AES_KEY+16(a0) 328 ld t1, OCTEON_CP2_AES_KEY+16(a0)
@@ -334,14 +334,14 @@
334 ld t1, OCTEON_CP2_AES_RESULT(a0) 334 ld t1, OCTEON_CP2_AES_RESULT(a0)
335 dmtc2 t2, 0x0107 335 dmtc2 t2, 0x0107
336 ld t2, OCTEON_CP2_AES_RESULT+8(a0) 336 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
337 mfc0 t3, $15,0 /* Get the processor ID register */ 337 mfc0 t3, $15,0 /* Get the processor ID register */
338 dmtc2 t0, 0x0110 338 dmtc2 t0, 0x0110
339 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 339 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
340 dmtc2 t1, 0x0100 340 dmtc2 t1, 0x0100
341 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ 341 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
342 dmtc2 t2, 0x0101 342 dmtc2 t2, 0x0101
343 343
344 /* this code is specific for pass 1 */ 344 /* this code is specific for pass 1 */
345 ld t0, OCTEON_CP2_HSH_DATW(a0) 345 ld t0, OCTEON_CP2_HSH_DATW(a0)
346 ld t1, OCTEON_CP2_HSH_DATW+8(a0) 346 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
347 ld t2, OCTEON_CP2_HSH_DATW+16(a0) 347 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
@@ -361,10 +361,10 @@
361 ld t0, OCTEON_CP2_HSH_IVW+16(a0) 361 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
362 dmtc2 t1, 0x0048 362 dmtc2 t1, 0x0048
363 dmtc2 t2, 0x0049 363 dmtc2 t2, 0x0049
364 b done_restore /* unconditional branch */ 364 b done_restore /* unconditional branch */
365 dmtc2 t0, 0x004A 365 dmtc2 t0, 0x004A
366 366
3673: /* this is post-pass1 code */ 3673: /* this is post-pass1 code */
368 ld t2, OCTEON_CP2_HSH_DATW(a0) 368 ld t2, OCTEON_CP2_HSH_DATW(a0)
369 ld t0, OCTEON_CP2_HSH_DATW+8(a0) 369 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
370 ld t1, OCTEON_CP2_HSH_DATW+16(a0) 370 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
@@ -433,7 +433,7 @@ done_restore:
433 * sp is assumed to point to a struct pt_regs 433 * sp is assumed to point to a struct pt_regs
434 * 434 *
435 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only 435 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
436 * safely modify k0 and k1. 436 * safely modify k0 and k1.
437 */ 437 */
438 .align 7 438 .align 7
439 .set push 439 .set push
@@ -446,14 +446,14 @@ done_restore:
446 /* Save the multiplier state */ 446 /* Save the multiplier state */
447 v3mulu k0, $0, $0 447 v3mulu k0, $0, $0
448 v3mulu k1, $0, $0 448 v3mulu k1, $0, $0
449 sd k0, PT_MTP(sp) /* PT_MTP has P0 */ 449 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
450 v3mulu k0, $0, $0 450 v3mulu k0, $0, $0
451 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ 451 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
452 ori k1, $0, 1 452 ori k1, $0, 1
453 v3mulu k1, k1, $0 453 v3mulu k1, k1, $0
454 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ 454 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
455 v3mulu k0, $0, $0 455 v3mulu k0, $0, $0
456 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ 456 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
457 v3mulu k1, $0, $0 457 v3mulu k1, $0, $0
458 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ 458 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
459 jr ra 459 jr ra
@@ -475,19 +475,19 @@ done_restore:
475 .set noreorder 475 .set noreorder
476 LEAF(octeon_mult_restore) 476 LEAF(octeon_mult_restore)
477 dmfc0 k1, $9,7 /* CvmCtl register. */ 477 dmfc0 k1, $9,7 /* CvmCtl register. */
478 ld v0, PT_MPL(sp) /* MPL0 */ 478 ld v0, PT_MPL(sp) /* MPL0 */
479 ld v1, PT_MPL+8(sp) /* MPL1 */ 479 ld v1, PT_MPL+8(sp) /* MPL1 */
480 ld k0, PT_MPL+16(sp) /* MPL2 */ 480 ld k0, PT_MPL+16(sp) /* MPL2 */
481 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ 481 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
482 /* Normally falls through, so no time wasted here */ 482 /* Normally falls through, so no time wasted here */
483 nop 483 nop
484 484
485 /* Restore the multiplier state */ 485 /* Restore the multiplier state */
486 ld k1, PT_MTP+16(sp) /* P2 */ 486 ld k1, PT_MTP+16(sp) /* P2 */
487 MTM0 v0 /* MPL0 */ 487 MTM0 v0 /* MPL0 */
488 ld v0, PT_MTP+8(sp) /* P1 */ 488 ld v0, PT_MTP+8(sp) /* P1 */
489 MTM1 v1 /* MPL1 */ 489 MTM1 v1 /* MPL1 */
490 ld v1, PT_MTP(sp) /* P0 */ 490 ld v1, PT_MTP(sp) /* P0 */
491 MTM2 k0 /* MPL2 */ 491 MTM2 k0 /* MPL2 */
492 MTP2 k1 /* P2 */ 492 MTP2 k1 /* P2 */
493 MTP1 v0 /* P1 */ 493 MTP1 v0 /* P1 */
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index d9c81c5a6c90..45f1ffcf1a4b 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -103,13 +103,13 @@ static struct mips_pmu mipspmu;
103 103
104#define M_CONFIG1_PC (1 << 4) 104#define M_CONFIG1_PC (1 << 4)
105 105
106#define M_PERFCTL_EXL (1 << 0) 106#define M_PERFCTL_EXL (1 << 0)
107#define M_PERFCTL_KERNEL (1 << 1) 107#define M_PERFCTL_KERNEL (1 << 1)
108#define M_PERFCTL_SUPERVISOR (1 << 2) 108#define M_PERFCTL_SUPERVISOR (1 << 2)
109#define M_PERFCTL_USER (1 << 3) 109#define M_PERFCTL_USER (1 << 3)
110#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) 110#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
111#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) 111#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
112#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 112#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
113 113
114#ifdef CONFIG_CPU_BMIPS5000 114#ifdef CONFIG_CPU_BMIPS5000
115#define M_PERFCTL_MT_EN(filter) 0 115#define M_PERFCTL_MT_EN(filter) 0
@@ -117,13 +117,13 @@ static struct mips_pmu mipspmu;
117#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 117#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
118#endif /* CONFIG_CPU_BMIPS5000 */ 118#endif /* CONFIG_CPU_BMIPS5000 */
119 119
120#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 120#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
121#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) 121#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
122#define M_TC_EN_TC M_PERFCTL_MT_EN(2) 122#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
123#define M_PERFCTL_TCID(tcid) ((tcid) << 22) 123#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
124#define M_PERFCTL_WIDE (1 << 30) 124#define M_PERFCTL_WIDE (1 << 30)
125#define M_PERFCTL_MORE (1 << 31) 125#define M_PERFCTL_MORE (1 << 31)
126#define M_PERFCTL_TC (1 << 30) 126#define M_PERFCTL_TC (1 << 30)
127 127
128#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ 128#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
129 M_PERFCTL_KERNEL | \ 129 M_PERFCTL_KERNEL | \
@@ -827,7 +827,7 @@ static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
827 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 827 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
828 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, 828 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
829 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, 829 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
830 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, 830 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
831 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, 831 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
832 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, 832 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
833 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, 833 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
@@ -1371,7 +1371,7 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1371 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ 1371 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1372 (r) == 176 || ((b) >= 50 && (b) <= 55) || \ 1372 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1373 ((b) >= 64 && (b) <= 67)) 1373 ((b) >= 64 && (b) <= 67))
1374#define IS_RANGE_V_34K_EVENT(r) ((r) == 47) 1374#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1375#endif 1375#endif
1376 1376
1377/* 74K */ 1377/* 74K */
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 07dff54f2ce8..9dafed058136 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle 2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc. 3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2004 Maciej W. Rozycki 4 * Copyright (C) 2004 Maciej W. Rozycki
5 */ 5 */
6#include <linux/delay.h> 6#include <linux/delay.h>
7#include <linux/kernel.h> 7#include <linux/kernel.h>
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index a11c6f9fdd5e..902e7803fcfa 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -154,8 +154,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
154 return 0; 154 return 0;
155 } 155 }
156 *childregs = *regs; 156 *childregs = *regs;
157 childregs->regs[7] = 0; /* Clear error flag */ 157 childregs->regs[7] = 0; /* Clear error flag */
158 childregs->regs[2] = 0; /* Child gets zero as return value */ 158 childregs->regs[2] = 0; /* Child gets zero as return value */
159 childregs->regs[29] = usp; 159 childregs->regs[29] = usp;
160 ti->addr_limit = USER_DS; 160 ti->addr_limit = USER_DS;
161 161
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 4812c6d916e4..9c6299c733a3 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -50,7 +50,7 @@ void ptrace_disable(struct task_struct *child)
50} 50}
51 51
52/* 52/*
53 * Read a general register set. We always use the 64-bit format, even 53 * Read a general register set. We always use the 64-bit format, even
54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. 54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
55 * Registers are sign extended to fill the available space. 55 * Registers are sign extended to fill the available space.
56 */ 56 */
@@ -326,7 +326,7 @@ long arch_ptrace(struct task_struct *child, long request,
326 case FPC_CSR: 326 case FPC_CSR:
327 tmp = child->thread.fpu.fcr31; 327 tmp = child->thread.fpu.fcr31;
328 break; 328 break;
329 case FPC_EIR: { /* implementation / version register */ 329 case FPC_EIR: { /* implementation / version register */
330 unsigned int flags; 330 unsigned int flags;
331#ifdef CONFIG_MIPS_MT_SMTC 331#ifdef CONFIG_MIPS_MT_SMTC
332 unsigned long irqflags; 332 unsigned long irqflags;
@@ -520,10 +520,10 @@ static inline int audit_arch(void)
520{ 520{
521 int arch = EM_MIPS; 521 int arch = EM_MIPS;
522#ifdef CONFIG_64BIT 522#ifdef CONFIG_64BIT
523 arch |= __AUDIT_ARCH_64BIT; 523 arch |= __AUDIT_ARCH_64BIT;
524#endif 524#endif
525#if defined(__LITTLE_ENDIAN) 525#if defined(__LITTLE_ENDIAN)
526 arch |= __AUDIT_ARCH_LE; 526 arch |= __AUDIT_ARCH_LE;
527#endif 527#endif
528 return arch; 528 return arch;
529} 529}
@@ -546,7 +546,7 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs)
546 /* The 0x80 provides a way for the tracing parent to distinguish 546 /* The 0x80 provides a way for the tracing parent to distinguish
547 between a syscall stop and SIGTRAP delivery */ 547 between a syscall stop and SIGTRAP delivery */
548 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 548 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
549 0x80 : 0)); 549 0x80 : 0));
550 550
551 /* 551 /*
552 * this isn't the same as continuing with a signal, but it will do 552 * this isn't the same as continuing with a signal, but it will do
@@ -581,7 +581,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
581 /* The 0x80 provides a way for the tracing parent to distinguish 581 /* The 0x80 provides a way for the tracing parent to distinguish
582 between a syscall stop and SIGTRAP delivery */ 582 between a syscall stop and SIGTRAP delivery */
583 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 583 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
584 0x80 : 0)); 584 0x80 : 0));
585 585
586 /* 586 /*
587 * this isn't the same as continuing with a signal, but it will do 587 * this isn't the same as continuing with a signal, but it will do
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index a3b017815eff..9486055ba660 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -124,7 +124,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
124 case FPC_CSR: 124 case FPC_CSR:
125 tmp = child->thread.fpu.fcr31; 125 tmp = child->thread.fpu.fcr31;
126 break; 126 break;
127 case FPC_EIR: { /* implementation / version register */ 127 case FPC_EIR: { /* implementation / version register */
128 unsigned int flags; 128 unsigned int flags;
129#ifdef CONFIG_MIPS_MT_SMTC 129#ifdef CONFIG_MIPS_MT_SMTC
130 unsigned int irqflags; 130 unsigned int irqflags;
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index 61c8a0f2a60c..f31063dbdaeb 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -30,38 +30,38 @@
30LEAF(_save_fp_context) 30LEAF(_save_fp_context)
31 li v0, 0 # assume success 31 li v0, 0 # assume success
32 cfc1 t1,fcr31 32 cfc1 t1,fcr31
33 EX(swc1 $f0,(SC_FPREGS+0)(a0)) 33 EX(swc1 $f0,(SC_FPREGS+0)(a0))
34 EX(swc1 $f1,(SC_FPREGS+8)(a0)) 34 EX(swc1 $f1,(SC_FPREGS+8)(a0))
35 EX(swc1 $f2,(SC_FPREGS+16)(a0)) 35 EX(swc1 $f2,(SC_FPREGS+16)(a0))
36 EX(swc1 $f3,(SC_FPREGS+24)(a0)) 36 EX(swc1 $f3,(SC_FPREGS+24)(a0))
37 EX(swc1 $f4,(SC_FPREGS+32)(a0)) 37 EX(swc1 $f4,(SC_FPREGS+32)(a0))
38 EX(swc1 $f5,(SC_FPREGS+40)(a0)) 38 EX(swc1 $f5,(SC_FPREGS+40)(a0))
39 EX(swc1 $f6,(SC_FPREGS+48)(a0)) 39 EX(swc1 $f6,(SC_FPREGS+48)(a0))
40 EX(swc1 $f7,(SC_FPREGS+56)(a0)) 40 EX(swc1 $f7,(SC_FPREGS+56)(a0))
41 EX(swc1 $f8,(SC_FPREGS+64)(a0)) 41 EX(swc1 $f8,(SC_FPREGS+64)(a0))
42 EX(swc1 $f9,(SC_FPREGS+72)(a0)) 42 EX(swc1 $f9,(SC_FPREGS+72)(a0))
43 EX(swc1 $f10,(SC_FPREGS+80)(a0)) 43 EX(swc1 $f10,(SC_FPREGS+80)(a0))
44 EX(swc1 $f11,(SC_FPREGS+88)(a0)) 44 EX(swc1 $f11,(SC_FPREGS+88)(a0))
45 EX(swc1 $f12,(SC_FPREGS+96)(a0)) 45 EX(swc1 $f12,(SC_FPREGS+96)(a0))
46 EX(swc1 $f13,(SC_FPREGS+104)(a0)) 46 EX(swc1 $f13,(SC_FPREGS+104)(a0))
47 EX(swc1 $f14,(SC_FPREGS+112)(a0)) 47 EX(swc1 $f14,(SC_FPREGS+112)(a0))
48 EX(swc1 $f15,(SC_FPREGS+120)(a0)) 48 EX(swc1 $f15,(SC_FPREGS+120)(a0))
49 EX(swc1 $f16,(SC_FPREGS+128)(a0)) 49 EX(swc1 $f16,(SC_FPREGS+128)(a0))
50 EX(swc1 $f17,(SC_FPREGS+136)(a0)) 50 EX(swc1 $f17,(SC_FPREGS+136)(a0))
51 EX(swc1 $f18,(SC_FPREGS+144)(a0)) 51 EX(swc1 $f18,(SC_FPREGS+144)(a0))
52 EX(swc1 $f19,(SC_FPREGS+152)(a0)) 52 EX(swc1 $f19,(SC_FPREGS+152)(a0))
53 EX(swc1 $f20,(SC_FPREGS+160)(a0)) 53 EX(swc1 $f20,(SC_FPREGS+160)(a0))
54 EX(swc1 $f21,(SC_FPREGS+168)(a0)) 54 EX(swc1 $f21,(SC_FPREGS+168)(a0))
55 EX(swc1 $f22,(SC_FPREGS+176)(a0)) 55 EX(swc1 $f22,(SC_FPREGS+176)(a0))
56 EX(swc1 $f23,(SC_FPREGS+184)(a0)) 56 EX(swc1 $f23,(SC_FPREGS+184)(a0))
57 EX(swc1 $f24,(SC_FPREGS+192)(a0)) 57 EX(swc1 $f24,(SC_FPREGS+192)(a0))
58 EX(swc1 $f25,(SC_FPREGS+200)(a0)) 58 EX(swc1 $f25,(SC_FPREGS+200)(a0))
59 EX(swc1 $f26,(SC_FPREGS+208)(a0)) 59 EX(swc1 $f26,(SC_FPREGS+208)(a0))
60 EX(swc1 $f27,(SC_FPREGS+216)(a0)) 60 EX(swc1 $f27,(SC_FPREGS+216)(a0))
61 EX(swc1 $f28,(SC_FPREGS+224)(a0)) 61 EX(swc1 $f28,(SC_FPREGS+224)(a0))
62 EX(swc1 $f29,(SC_FPREGS+232)(a0)) 62 EX(swc1 $f29,(SC_FPREGS+232)(a0))
63 EX(swc1 $f30,(SC_FPREGS+240)(a0)) 63 EX(swc1 $f30,(SC_FPREGS+240)(a0))
64 EX(swc1 $f31,(SC_FPREGS+248)(a0)) 64 EX(swc1 $f31,(SC_FPREGS+248)(a0))
65 EX(sw t1,(SC_FPC_CSR)(a0)) 65 EX(sw t1,(SC_FPC_CSR)(a0))
66 cfc1 t0,$0 # implementation/version 66 cfc1 t0,$0 # implementation/version
67 jr ra 67 jr ra
@@ -82,38 +82,38 @@ LEAF(_save_fp_context)
82LEAF(_restore_fp_context) 82LEAF(_restore_fp_context)
83 li v0, 0 # assume success 83 li v0, 0 # assume success
84 EX(lw t0,(SC_FPC_CSR)(a0)) 84 EX(lw t0,(SC_FPC_CSR)(a0))
85 EX(lwc1 $f0,(SC_FPREGS+0)(a0)) 85 EX(lwc1 $f0,(SC_FPREGS+0)(a0))
86 EX(lwc1 $f1,(SC_FPREGS+8)(a0)) 86 EX(lwc1 $f1,(SC_FPREGS+8)(a0))
87 EX(lwc1 $f2,(SC_FPREGS+16)(a0)) 87 EX(lwc1 $f2,(SC_FPREGS+16)(a0))
88 EX(lwc1 $f3,(SC_FPREGS+24)(a0)) 88 EX(lwc1 $f3,(SC_FPREGS+24)(a0))
89 EX(lwc1 $f4,(SC_FPREGS+32)(a0)) 89 EX(lwc1 $f4,(SC_FPREGS+32)(a0))
90 EX(lwc1 $f5,(SC_FPREGS+40)(a0)) 90 EX(lwc1 $f5,(SC_FPREGS+40)(a0))
91 EX(lwc1 $f6,(SC_FPREGS+48)(a0)) 91 EX(lwc1 $f6,(SC_FPREGS+48)(a0))
92 EX(lwc1 $f7,(SC_FPREGS+56)(a0)) 92 EX(lwc1 $f7,(SC_FPREGS+56)(a0))
93 EX(lwc1 $f8,(SC_FPREGS+64)(a0)) 93 EX(lwc1 $f8,(SC_FPREGS+64)(a0))
94 EX(lwc1 $f9,(SC_FPREGS+72)(a0)) 94 EX(lwc1 $f9,(SC_FPREGS+72)(a0))
95 EX(lwc1 $f10,(SC_FPREGS+80)(a0)) 95 EX(lwc1 $f10,(SC_FPREGS+80)(a0))
96 EX(lwc1 $f11,(SC_FPREGS+88)(a0)) 96 EX(lwc1 $f11,(SC_FPREGS+88)(a0))
97 EX(lwc1 $f12,(SC_FPREGS+96)(a0)) 97 EX(lwc1 $f12,(SC_FPREGS+96)(a0))
98 EX(lwc1 $f13,(SC_FPREGS+104)(a0)) 98 EX(lwc1 $f13,(SC_FPREGS+104)(a0))
99 EX(lwc1 $f14,(SC_FPREGS+112)(a0)) 99 EX(lwc1 $f14,(SC_FPREGS+112)(a0))
100 EX(lwc1 $f15,(SC_FPREGS+120)(a0)) 100 EX(lwc1 $f15,(SC_FPREGS+120)(a0))
101 EX(lwc1 $f16,(SC_FPREGS+128)(a0)) 101 EX(lwc1 $f16,(SC_FPREGS+128)(a0))
102 EX(lwc1 $f17,(SC_FPREGS+136)(a0)) 102 EX(lwc1 $f17,(SC_FPREGS+136)(a0))
103 EX(lwc1 $f18,(SC_FPREGS+144)(a0)) 103 EX(lwc1 $f18,(SC_FPREGS+144)(a0))
104 EX(lwc1 $f19,(SC_FPREGS+152)(a0)) 104 EX(lwc1 $f19,(SC_FPREGS+152)(a0))
105 EX(lwc1 $f20,(SC_FPREGS+160)(a0)) 105 EX(lwc1 $f20,(SC_FPREGS+160)(a0))
106 EX(lwc1 $f21,(SC_FPREGS+168)(a0)) 106 EX(lwc1 $f21,(SC_FPREGS+168)(a0))
107 EX(lwc1 $f22,(SC_FPREGS+176)(a0)) 107 EX(lwc1 $f22,(SC_FPREGS+176)(a0))
108 EX(lwc1 $f23,(SC_FPREGS+184)(a0)) 108 EX(lwc1 $f23,(SC_FPREGS+184)(a0))
109 EX(lwc1 $f24,(SC_FPREGS+192)(a0)) 109 EX(lwc1 $f24,(SC_FPREGS+192)(a0))
110 EX(lwc1 $f25,(SC_FPREGS+200)(a0)) 110 EX(lwc1 $f25,(SC_FPREGS+200)(a0))
111 EX(lwc1 $f26,(SC_FPREGS+208)(a0)) 111 EX(lwc1 $f26,(SC_FPREGS+208)(a0))
112 EX(lwc1 $f27,(SC_FPREGS+216)(a0)) 112 EX(lwc1 $f27,(SC_FPREGS+216)(a0))
113 EX(lwc1 $f28,(SC_FPREGS+224)(a0)) 113 EX(lwc1 $f28,(SC_FPREGS+224)(a0))
114 EX(lwc1 $f29,(SC_FPREGS+232)(a0)) 114 EX(lwc1 $f29,(SC_FPREGS+232)(a0))
115 EX(lwc1 $f30,(SC_FPREGS+240)(a0)) 115 EX(lwc1 $f30,(SC_FPREGS+240)(a0))
116 EX(lwc1 $f31,(SC_FPREGS+248)(a0)) 116 EX(lwc1 $f31,(SC_FPREGS+248)(a0))
117 jr ra 117 jr ra
118 ctc1 t0,fcr31 118 ctc1 t0,fcr31
119 END(_restore_fp_context) 119 END(_restore_fp_context)
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 8d32d5a6b460..5266c6ee2b35 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -42,7 +42,7 @@
42 42
43/* 43/*
44 * task_struct *resume(task_struct *prev, task_struct *next, 44 * task_struct *resume(task_struct *prev, task_struct *next,
45 * struct thread_info *next_ti, int usedfpu) 45 * struct thread_info *next_ti, int usedfpu)
46 */ 46 */
47LEAF(resume) 47LEAF(resume)
48 mfc0 t1, CP0_STATUS 48 mfc0 t1, CP0_STATUS
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 8decdfacb448..5e51219990aa 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -40,7 +40,7 @@
40 40
41/* 41/*
42 * task_struct *resume(task_struct *prev, task_struct *next, 42 * task_struct *resume(task_struct *prev, task_struct *next,
43 * struct thread_info *next_ti, int usedfpu) 43 * struct thread_info *next_ti, int usedfpu)
44 */ 44 */
45 .align 5 45 .align 5
46 LEAF(resume) 46 LEAF(resume)
@@ -53,7 +53,7 @@
53 * check if we need to save FPU registers 53 * check if we need to save FPU registers
54 */ 54 */
55 55
56 beqz a3, 1f 56 beqz a3, 1f
57 57
58 PTR_L t3, TASK_THREAD_INFO(a0) 58 PTR_L t3, TASK_THREAD_INFO(a0)
59 /* 59 /*
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 804ebb2c34a6..43d2d78d3287 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -33,7 +33,7 @@ process_entry:
33 b process_entry 33 b process_entry
34 34
351: 351:
36 /* indirection page, update s0 */ 36 /* indirection page, update s0 */
37 and s3, s2, 0x2 37 and s3, s2, 0x2
38 beq s3, zero, 1f 38 beq s3, zero, 1f
39 and s0, s2, ~0x2 39 and s0, s2, ~0x2
@@ -69,7 +69,7 @@ done:
69 of kexec_flag. */ 69 of kexec_flag. */
70 70
71 bal 1f 71 bal 1f
72 1: move t1,ra; 72 1: move t1,ra;
73 PTR_LA t2,1b 73 PTR_LA t2,1b
74 PTR_LA t0,kexec_flag 74 PTR_LA t0,kexec_flag
75 PTR_SUB t0,t0,t2; 75 PTR_SUB t0,t0,t2;
@@ -158,10 +158,10 @@ arg3: PTR 0x0
158 */ 158 */
159secondary_kexec_args: 159secondary_kexec_args:
160 EXPORT(secondary_kexec_args) 160 EXPORT(secondary_kexec_args)
161s_arg0: PTR 0x0 161s_arg0: PTR 0x0
162s_arg1: PTR 0x0 162s_arg1: PTR 0x0
163s_arg2: PTR 0x0 163s_arg2: PTR 0x0
164s_arg3: PTR 0x0 164s_arg3: PTR 0x0
165 .size secondary_kexec_args,PTRSIZE*4 165 .size secondary_kexec_args,PTRSIZE*4
166kexec_flag: 166kexec_flag:
167 LONG 0x1 167 LONG 0x1
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index b8c18dcdd2c4..ce72bfff5e29 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -252,12 +252,12 @@ int rtlx_release(int index)
252 252
253unsigned int rtlx_read_poll(int index, int can_sleep) 253unsigned int rtlx_read_poll(int index, int can_sleep)
254{ 254{
255 struct rtlx_channel *chan; 255 struct rtlx_channel *chan;
256 256
257 if (rtlx == NULL) 257 if (rtlx == NULL)
258 return 0; 258 return 0;
259 259
260 chan = &rtlx->channel[index]; 260 chan = &rtlx->channel[index];
261 261
262 /* data available to read? */ 262 /* data available to read? */
263 if (chan->lx_read == chan->lx_write) { 263 if (chan->lx_read == chan->lx_write) {
@@ -451,8 +451,8 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
451 return -EAGAIN; 451 return -EAGAIN;
452 452
453 __wait_event_interruptible(channel_wqs[minor].rt_queue, 453 __wait_event_interruptible(channel_wqs[minor].rt_queue,
454 rtlx_write_poll(minor), 454 rtlx_write_poll(minor),
455 ret); 455 ret);
456 if (ret) 456 if (ret)
457 return ret; 457 return ret;
458 } 458 }
@@ -462,11 +462,11 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
462 462
463static const struct file_operations rtlx_fops = { 463static const struct file_operations rtlx_fops = {
464 .owner = THIS_MODULE, 464 .owner = THIS_MODULE,
465 .open = file_open, 465 .open = file_open,
466 .release = file_release, 466 .release = file_release,
467 .write = file_write, 467 .write = file_write,
468 .read = file_read, 468 .read = file_read,
469 .poll = file_poll, 469 .poll = file_poll,
470 .llseek = noop_llseek, 470 .llseek = noop_llseek,
471}; 471};
472 472
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index d20a4bc9ed05..988bc06ff96e 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -24,7 +24,7 @@
24/* Highest syscall used of any syscall flavour */ 24/* Highest syscall used of any syscall flavour */
25#define MAX_SYSCALL_NO __NR_O32_Linux + __NR_O32_Linux_syscalls 25#define MAX_SYSCALL_NO __NR_O32_Linux + __NR_O32_Linux_syscalls
26 26
27 .align 5 27 .align 5
28NESTED(handle_sys, PT_SIZE, sp) 28NESTED(handle_sys, PT_SIZE, sp)
29 .set noat 29 .set noat
30 SAVE_SOME 30 SAVE_SOME
@@ -54,7 +54,7 @@ stack_done:
54 lw t0, TI_FLAGS($28) # syscall tracing enabled? 54 lw t0, TI_FLAGS($28) # syscall tracing enabled?
55 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 55 li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
56 and t0, t1 56 and t0, t1
57 bnez t0, syscall_trace_entry # -> yes 57 bnez t0, syscall_trace_entry # -> yes
58 58
59 jalr t2 # Do The Real Thing (TM) 59 jalr t2 # Do The Real Thing (TM)
60 60
@@ -126,8 +126,8 @@ stackargs:
126 la t1, 5f # load up to 3 arguments 126 la t1, 5f # load up to 3 arguments
127 subu t1, t3 127 subu t1, t3
1281: lw t5, 16(t0) # argument #5 from usp 1281: lw t5, 16(t0) # argument #5 from usp
129 .set push 129 .set push
130 .set noreorder 130 .set noreorder
131 .set nomacro 131 .set nomacro
132 jr t1 132 jr t1
133 addiu t1, 6f - 5f 133 addiu t1, 6f - 5f
@@ -205,7 +205,7 @@ illegal_syscall:
205 jr t2 205 jr t2
206 /* Unreached */ 206 /* Unreached */
207 207
208einval: li v0, -ENOSYS 208einval: li v0, -ENOSYS
209 jr ra 209 jr ra
210 END(sys_syscall) 210 END(sys_syscall)
211 211
@@ -354,7 +354,7 @@ einval: li v0, -ENOSYS
354 sys sys_ni_syscall 0 /* was create_module */ 354 sys sys_ni_syscall 0 /* was create_module */
355 sys sys_init_module 5 355 sys sys_init_module 5
356 sys sys_delete_module 1 356 sys sys_delete_module 1
357 sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */ 357 sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */
358 sys sys_quotactl 4 358 sys sys_quotactl 4
359 sys sys_getpgid 1 359 sys sys_getpgid 1
360 sys sys_fchdir 1 360 sys sys_fchdir 1
@@ -589,7 +589,7 @@ einval: li v0, -ENOSYS
589 /* We pre-compute the number of _instruction_ bytes needed to 589 /* We pre-compute the number of _instruction_ bytes needed to
590 load or store the arguments 6-8. Negative values are ignored. */ 590 load or store the arguments 6-8. Negative values are ignored. */
591 591
592 .macro sys function, nargs 592 .macro sys function, nargs
593 PTR \function 593 PTR \function
594 LONG (\nargs << 2) - (5 << 2) 594 LONG (\nargs << 2) - (5 << 2)
595 .endm 595 .endm
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index b64f642da073..4c356b0093cf 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -25,7 +25,7 @@
25#define handle_sys64 handle_sys 25#define handle_sys64 handle_sys
26#endif 26#endif
27 27
28 .align 5 28 .align 5
29NESTED(handle_sys64, PT_SIZE, sp) 29NESTED(handle_sys64, PT_SIZE, sp)
30#if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32) 30#if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
31 /* 31 /*
@@ -40,7 +40,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
40#endif 40#endif
41 41
42 dsubu t0, v0, __NR_64_Linux # check syscall number 42 dsubu t0, v0, __NR_64_Linux # check syscall number
43 sltiu t0, t0, __NR_64_Linux_syscalls + 1 43 sltiu t0, t0, __NR_64_Linux_syscalls + 1
44#if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32) 44#if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
45 ld t1, PT_EPC(sp) # skip syscall on return 45 ld t1, PT_EPC(sp) # skip syscall on return
46 daddiu t1, 4 # skip to next instruction 46 daddiu t1, 4 # skip to next instruction
@@ -290,7 +290,7 @@ sys_call_table:
290 PTR sys_quotactl 290 PTR sys_quotactl
291 PTR sys_ni_syscall /* was nfsservctl */ 291 PTR sys_ni_syscall /* was nfsservctl */
292 PTR sys_ni_syscall /* res. for getpmsg */ 292 PTR sys_ni_syscall /* res. for getpmsg */
293 PTR sys_ni_syscall /* 5175 for putpmsg */ 293 PTR sys_ni_syscall /* 5175 for putpmsg */
294 PTR sys_ni_syscall /* res. for afs_syscall */ 294 PTR sys_ni_syscall /* res. for afs_syscall */
295 PTR sys_ni_syscall /* res. for security */ 295 PTR sys_ni_syscall /* res. for security */
296 PTR sys_gettid 296 PTR sys_gettid
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index c29ac197f446..30ef88b989af 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -22,7 +22,7 @@
22#define handle_sysn32 handle_sys 22#define handle_sysn32 handle_sys
23#endif 23#endif
24 24
25 .align 5 25 .align 5
26NESTED(handle_sysn32, PT_SIZE, sp) 26NESTED(handle_sysn32, PT_SIZE, sp)
27#ifndef CONFIG_MIPS32_O32 27#ifndef CONFIG_MIPS32_O32
28 .set noat 28 .set noat
@@ -33,7 +33,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
33#endif 33#endif
34 34
35 dsubu t0, v0, __NR_N32_Linux # check syscall number 35 dsubu t0, v0, __NR_N32_Linux # check syscall number
36 sltiu t0, t0, __NR_N32_Linux_syscalls + 1 36 sltiu t0, t0, __NR_N32_Linux_syscalls + 1
37 37
38#ifndef CONFIG_MIPS32_O32 38#ifndef CONFIG_MIPS32_O32
39 ld t1, PT_EPC(sp) # skip syscall on return 39 ld t1, PT_EPC(sp) # skip syscall on return
@@ -279,7 +279,7 @@ EXPORT(sysn32_call_table)
279 PTR sys_quotactl 279 PTR sys_quotactl
280 PTR sys_ni_syscall /* was nfsservctl */ 280 PTR sys_ni_syscall /* was nfsservctl */
281 PTR sys_ni_syscall /* res. for getpmsg */ 281 PTR sys_ni_syscall /* res. for getpmsg */
282 PTR sys_ni_syscall /* 6175 for putpmsg */ 282 PTR sys_ni_syscall /* 6175 for putpmsg */
283 PTR sys_ni_syscall /* res. for afs_syscall */ 283 PTR sys_ni_syscall /* res. for afs_syscall */
284 PTR sys_ni_syscall /* res. for security */ 284 PTR sys_ni_syscall /* res. for security */
285 PTR sys_gettid 285 PTR sys_gettid
@@ -402,8 +402,8 @@ EXPORT(sysn32_call_table)
402 PTR compat_sys_rt_tgsigqueueinfo /* 6295 */ 402 PTR compat_sys_rt_tgsigqueueinfo /* 6295 */
403 PTR sys_perf_event_open 403 PTR sys_perf_event_open
404 PTR sys_accept4 404 PTR sys_accept4
405 PTR compat_sys_recvmmsg 405 PTR compat_sys_recvmmsg
406 PTR sys_getdents64 406 PTR sys_getdents64
407 PTR sys_fanotify_init /* 6300 */ 407 PTR sys_fanotify_init /* 6300 */
408 PTR sys_fanotify_mark 408 PTR sys_fanotify_mark
409 PTR sys_prlimit64 409 PTR sys_prlimit64
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index cf3e75e46650..42e789562db4 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -10,7 +10,7 @@
10 * 10 *
11 * Hairy, the userspace application uses a different argument passing 11 * Hairy, the userspace application uses a different argument passing
12 * convention than the kernel, so we have to translate things from o32 12 * convention than the kernel, so we have to translate things from o32
13 * to ABI64 calling convention. 64-bit syscalls are also processed 13 * to ABI64 calling convention. 64-bit syscalls are also processed
14 * here for now. 14 * here for now.
15 */ 15 */
16#include <linux/errno.h> 16#include <linux/errno.h>
@@ -24,7 +24,7 @@
24#include <asm/unistd.h> 24#include <asm/unistd.h>
25#include <asm/sysmips.h> 25#include <asm/sysmips.h>
26 26
27 .align 5 27 .align 5
28NESTED(handle_sys, PT_SIZE, sp) 28NESTED(handle_sys, PT_SIZE, sp)
29 .set noat 29 .set noat
30 SAVE_SOME 30 SAVE_SOME
@@ -185,7 +185,7 @@ LEAF(sys32_syscall)
185 jr t2 185 jr t2
186 /* Unreached */ 186 /* Unreached */
187 187
188einval: li v0, -ENOSYS 188einval: li v0, -ENOSYS
189 jr ra 189 jr ra
190 END(sys32_syscall) 190 END(sys32_syscall)
191 191
@@ -329,7 +329,7 @@ sys_call_table:
329 PTR sys_bdflush 329 PTR sys_bdflush
330 PTR sys_sysfs /* 4135 */ 330 PTR sys_sysfs /* 4135 */
331 PTR sys_32_personality 331 PTR sys_32_personality
332 PTR sys_ni_syscall /* for afs_syscall */ 332 PTR sys_ni_syscall /* for afs_syscall */
333 PTR sys_setfsuid 333 PTR sys_setfsuid
334 PTR sys_setfsgid 334 PTR sys_setfsgid
335 PTR sys_32_llseek /* 4140 */ 335 PTR sys_32_llseek /* 4140 */
@@ -352,12 +352,12 @@ sys_call_table:
352 PTR sys_munlockall 352 PTR sys_munlockall
353 PTR sys_sched_setparam 353 PTR sys_sched_setparam
354 PTR sys_sched_getparam 354 PTR sys_sched_getparam
355 PTR sys_sched_setscheduler /* 4160 */ 355 PTR sys_sched_setscheduler /* 4160 */
356 PTR sys_sched_getscheduler 356 PTR sys_sched_getscheduler
357 PTR sys_sched_yield 357 PTR sys_sched_yield
358 PTR sys_sched_get_priority_max 358 PTR sys_sched_get_priority_max
359 PTR sys_sched_get_priority_min 359 PTR sys_sched_get_priority_min
360 PTR sys_32_sched_rr_get_interval /* 4165 */ 360 PTR sys_32_sched_rr_get_interval /* 4165 */
361 PTR compat_sys_nanosleep 361 PTR compat_sys_nanosleep
362 PTR sys_mremap 362 PTR sys_mremap
363 PTR sys_accept 363 PTR sys_accept
@@ -387,7 +387,7 @@ sys_call_table:
387 PTR sys_prctl 387 PTR sys_prctl
388 PTR sys32_rt_sigreturn 388 PTR sys32_rt_sigreturn
389 PTR sys_32_rt_sigaction 389 PTR sys_32_rt_sigaction
390 PTR sys_32_rt_sigprocmask /* 4195 */ 390 PTR sys_32_rt_sigprocmask /* 4195 */
391 PTR sys_32_rt_sigpending 391 PTR sys_32_rt_sigpending
392 PTR compat_sys_rt_sigtimedwait 392 PTR compat_sys_rt_sigtimedwait
393 PTR sys_32_rt_sigqueueinfo 393 PTR sys_32_rt_sigqueueinfo
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8c41187801ce..653197e151d5 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -8,7 +8,7 @@
8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle 8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle
9 * Copyright (C) 1996 Stoned Elipot 9 * Copyright (C) 1996 Stoned Elipot
10 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki 11 * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
@@ -449,7 +449,7 @@ static void __init bootmem_init(void)
449 * At this stage the bootmem allocator is ready to use. 449 * At this stage the bootmem allocator is ready to use.
450 * 450 *
451 * NOTE: historically plat_mem_setup did the entire platform initialization. 451 * NOTE: historically plat_mem_setup did the entire platform initialization.
452 * This was rather impractical because it meant plat_mem_setup had to 452 * This was rather impractical because it meant plat_mem_setup had to
453 * get away without any kind of memory allocator. To keep old code from 453 * get away without any kind of memory allocator. To keep old code from
454 * breaking plat_setup was just renamed to plat_setup and a second platform 454 * breaking plat_setup was just renamed to plat_setup and a second platform
455 * initialization hook for anything else was introduced. 455 * initialization hook for anything else was introduced.
@@ -469,7 +469,7 @@ static int __init early_parse_mem(char *p)
469 if (usermem == 0) { 469 if (usermem == 0) {
470 boot_mem_map.nr_map = 0; 470 boot_mem_map.nr_map = 0;
471 usermem = 1; 471 usermem = 1;
472 } 472 }
473 start = 0; 473 start = 0;
474 size = memparse(p, &p); 474 size = memparse(p, &p);
475 if (*p == '@') 475 if (*p == '@')
@@ -571,7 +571,7 @@ static void __init mips_parse_crashkernel(void)
571 return; 571 return;
572 572
573 crashk_res.start = crash_base; 573 crashk_res.start = crash_base;
574 crashk_res.end = crash_base + crash_size - 1; 574 crashk_res.end = crash_base + crash_size - 1;
575} 575}
576 576
577static void __init request_crashkernel(struct resource *res) 577static void __init request_crashkernel(struct resource *res)
@@ -585,7 +585,7 @@ static void __init request_crashkernel(struct resource *res)
585 crashk_res.start + 1) >> 20), 585 crashk_res.start + 1) >> 20),
586 (unsigned long)(crashk_res.start >> 20)); 586 (unsigned long)(crashk_res.start >> 20));
587} 587}
588#else /* !defined(CONFIG_KEXEC) */ 588#else /* !defined(CONFIG_KEXEC) */
589static void __init mips_parse_crashkernel(void) 589static void __init mips_parse_crashkernel(void)
590{ 590{
591} 591}
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index b6aa77035019..0f57e06b7fdd 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -445,7 +445,7 @@ give_sigsegv:
445#endif 445#endif
446 446
447static int setup_rt_frame(void *sig_return, struct k_sigaction *ka, 447static int setup_rt_frame(void *sig_return, struct k_sigaction *ka,
448 struct pt_regs *regs, int signr, sigset_t *set, 448 struct pt_regs *regs, int signr, sigset_t *set,
449 siginfo_t *info) 449 siginfo_t *info)
450{ 450{
451 struct rt_sigframe __user *frame; 451 struct rt_sigframe __user *frame;
@@ -458,15 +458,15 @@ static int setup_rt_frame(void *sig_return, struct k_sigaction *ka,
458 /* Create siginfo. */ 458 /* Create siginfo. */
459 err |= copy_siginfo_to_user(&frame->rs_info, info); 459 err |= copy_siginfo_to_user(&frame->rs_info, info);
460 460
461 /* Create the ucontext. */ 461 /* Create the ucontext. */
462 err |= __put_user(0, &frame->rs_uc.uc_flags); 462 err |= __put_user(0, &frame->rs_uc.uc_flags);
463 err |= __put_user(NULL, &frame->rs_uc.uc_link); 463 err |= __put_user(NULL, &frame->rs_uc.uc_link);
464 err |= __put_user((void __user *)current->sas_ss_sp, 464 err |= __put_user((void __user *)current->sas_ss_sp,
465 &frame->rs_uc.uc_stack.ss_sp); 465 &frame->rs_uc.uc_stack.ss_sp);
466 err |= __put_user(sas_ss_flags(regs->regs[29]), 466 err |= __put_user(sas_ss_flags(regs->regs[29]),
467 &frame->rs_uc.uc_stack.ss_flags); 467 &frame->rs_uc.uc_stack.ss_flags);
468 err |= __put_user(current->sas_ss_size, 468 err |= __put_user(current->sas_ss_size,
469 &frame->rs_uc.uc_stack.ss_size); 469 &frame->rs_uc.uc_stack.ss_size);
470 err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext); 470 err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
471 err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set)); 471 err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set));
472 472
@@ -506,7 +506,7 @@ struct mips_abi mips_abi = {
506 .setup_frame = setup_frame, 506 .setup_frame = setup_frame,
507 .signal_return_offset = offsetof(struct mips_vdso, signal_trampoline), 507 .signal_return_offset = offsetof(struct mips_vdso, signal_trampoline),
508#endif 508#endif
509 .setup_rt_frame = setup_rt_frame, 509 .setup_rt_frame = setup_rt_frame,
510 .rt_signal_return_offset = 510 .rt_signal_return_offset =
511 offsetof(struct mips_vdso, rt_signal_trampoline), 511 offsetof(struct mips_vdso, rt_signal_trampoline),
512 .restart = __NR_restart_syscall 512 .restart = __NR_restart_syscall
@@ -538,7 +538,7 @@ static void handle_signal(unsigned long sig, siginfo_t *info,
538 regs->cp0_epc -= 4; 538 regs->cp0_epc -= 4;
539 } 539 }
540 540
541 regs->regs[0] = 0; /* Don't deal with this again. */ 541 regs->regs[0] = 0; /* Don't deal with this again. */
542 } 542 }
543 543
544 if (sig_uses_siginfo(ka)) 544 if (sig_uses_siginfo(ka))
@@ -562,7 +562,7 @@ static void do_signal(struct pt_regs *regs)
562 562
563 signr = get_signal_to_deliver(&info, &ka, regs, NULL); 563 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
564 if (signr > 0) { 564 if (signr > 0) {
565 /* Whee! Actually deliver the signal. */ 565 /* Whee! Actually deliver the signal. */
566 handle_signal(signr, &info, &ka, regs); 566 handle_signal(signr, &info, &ka, regs);
567 return; 567 return;
568 } 568 }
@@ -583,7 +583,7 @@ static void do_signal(struct pt_regs *regs)
583 regs->cp0_epc -= 4; 583 regs->cp0_epc -= 4;
584 break; 584 break;
585 } 585 }
586 regs->regs[0] = 0; /* Don't deal with this again. */ 586 regs->regs[0] = 0; /* Don't deal with this again. */
587 } 587 }
588 588
589 /* 589 /*
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index da1b56a39ac7..cae0b0e42a53 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -48,7 +48,7 @@ extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user
48/* 48/*
49 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ... 49 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
50 */ 50 */
51#define __NR_O32_restart_syscall 4253 51#define __NR_O32_restart_syscall 4253
52 52
53/* 32-bit compatibility types */ 53/* 32-bit compatibility types */
54 54
@@ -69,11 +69,11 @@ typedef struct sigaltstack32 {
69} stack32_t; 69} stack32_t;
70 70
71struct ucontext32 { 71struct ucontext32 {
72 u32 uc_flags; 72 u32 uc_flags;
73 s32 uc_link; 73 s32 uc_link;
74 stack32_t uc_stack; 74 stack32_t uc_stack;
75 struct sigcontext32 uc_mcontext; 75 struct sigcontext32 uc_mcontext;
76 compat_sigset_t uc_sigmask; /* mask last for extensibility */ 76 compat_sigset_t uc_sigmask; /* mask last for extensibility */
77}; 77};
78 78
79struct sigframe32 { 79struct sigframe32 {
@@ -338,7 +338,7 @@ SYSCALL_DEFINE3(32_sigaction, long, sig, const struct sigaction32 __user *, act,
338 return -EFAULT; 338 return -EFAULT;
339 err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); 339 err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
340 err |= __put_user((u32)(u64)old_ka.sa.sa_handler, 340 err |= __put_user((u32)(u64)old_ka.sa.sa_handler,
341 &oact->sa_handler); 341 &oact->sa_handler);
342 err |= __put_user(old_ka.sa.sa_mask.sig[0], oact->sa_mask.sig); 342 err |= __put_user(old_ka.sa.sa_mask.sig[0], oact->sa_mask.sig);
343 err |= __put_user(0, &oact->sa_mask.sig[1]); 343 err |= __put_user(0, &oact->sa_mask.sig[1]);
344 err |= __put_user(0, &oact->sa_mask.sig[2]); 344 err |= __put_user(0, &oact->sa_mask.sig[2]);
@@ -599,16 +599,16 @@ static int setup_rt_frame_32(void *sig_return, struct k_sigaction *ka,
599 /* Convert (siginfo_t -> compat_siginfo_t) and copy to user. */ 599 /* Convert (siginfo_t -> compat_siginfo_t) and copy to user. */
600 err |= copy_siginfo_to_user32(&frame->rs_info, info); 600 err |= copy_siginfo_to_user32(&frame->rs_info, info);
601 601
602 /* Create the ucontext. */ 602 /* Create the ucontext. */
603 err |= __put_user(0, &frame->rs_uc.uc_flags); 603 err |= __put_user(0, &frame->rs_uc.uc_flags);
604 err |= __put_user(0, &frame->rs_uc.uc_link); 604 err |= __put_user(0, &frame->rs_uc.uc_link);
605 sp = (int) (long) current->sas_ss_sp; 605 sp = (int) (long) current->sas_ss_sp;
606 err |= __put_user(sp, 606 err |= __put_user(sp,
607 &frame->rs_uc.uc_stack.ss_sp); 607 &frame->rs_uc.uc_stack.ss_sp);
608 err |= __put_user(sas_ss_flags(regs->regs[29]), 608 err |= __put_user(sas_ss_flags(regs->regs[29]),
609 &frame->rs_uc.uc_stack.ss_flags); 609 &frame->rs_uc.uc_stack.ss_flags);
610 err |= __put_user(current->sas_ss_size, 610 err |= __put_user(current->sas_ss_size,
611 &frame->rs_uc.uc_stack.ss_size); 611 &frame->rs_uc.uc_stack.ss_size);
612 err |= setup_sigcontext32(regs, &frame->rs_uc.uc_mcontext); 612 err |= setup_sigcontext32(regs, &frame->rs_uc.uc_mcontext);
613 err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set); 613 err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
614 614
@@ -650,7 +650,7 @@ struct mips_abi mips_abi_32 = {
650 .setup_frame = setup_frame_32, 650 .setup_frame = setup_frame_32,
651 .signal_return_offset = 651 .signal_return_offset =
652 offsetof(struct mips_vdso, o32_signal_trampoline), 652 offsetof(struct mips_vdso, o32_signal_trampoline),
653 .setup_rt_frame = setup_rt_frame_32, 653 .setup_rt_frame = setup_rt_frame_32,
654 .rt_signal_return_offset = 654 .rt_signal_return_offset =
655 offsetof(struct mips_vdso, o32_rt_signal_trampoline), 655 offsetof(struct mips_vdso, o32_rt_signal_trampoline),
656 .restart = __NR_O32_restart_syscall 656 .restart = __NR_O32_restart_syscall
@@ -690,7 +690,7 @@ SYSCALL_DEFINE4(32_rt_sigaction, int, sig,
690 return -EFAULT; 690 return -EFAULT;
691 691
692 err |= __put_user((u32)(u64)old_sa.sa.sa_handler, 692 err |= __put_user((u32)(u64)old_sa.sa.sa_handler,
693 &oact->sa_handler); 693 &oact->sa_handler);
694 err |= __put_user(old_sa.sa.sa_flags, &oact->sa_flags); 694 err |= __put_user(old_sa.sa.sa_flags, &oact->sa_flags);
695 err |= put_sigset(&old_sa.sa.sa_mask, &oact->sa_mask); 695 err |= put_sigset(&old_sa.sa.sa_mask, &oact->sa_mask);
696 if (err) 696 if (err)
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 3574c145511b..7246e33721ae 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -59,11 +59,11 @@ typedef struct sigaltstack32 {
59} stack32_t; 59} stack32_t;
60 60
61struct ucontextn32 { 61struct ucontextn32 {
62 u32 uc_flags; 62 u32 uc_flags;
63 s32 uc_link; 63 s32 uc_link;
64 stack32_t uc_stack; 64 stack32_t uc_stack;
65 struct sigcontext uc_mcontext; 65 struct sigcontext uc_mcontext;
66 compat_sigset_t uc_sigmask; /* mask last for extensibility */ 66 compat_sigset_t uc_sigmask; /* mask last for extensibility */
67}; 67};
68 68
69struct rt_sigframe_n32 { 69struct rt_sigframe_n32 {
@@ -162,16 +162,16 @@ static int setup_rt_frame_n32(void *sig_return, struct k_sigaction *ka,
162 /* Create siginfo. */ 162 /* Create siginfo. */
163 err |= copy_siginfo_to_user32(&frame->rs_info, info); 163 err |= copy_siginfo_to_user32(&frame->rs_info, info);
164 164
165 /* Create the ucontext. */ 165 /* Create the ucontext. */
166 err |= __put_user(0, &frame->rs_uc.uc_flags); 166 err |= __put_user(0, &frame->rs_uc.uc_flags);
167 err |= __put_user(0, &frame->rs_uc.uc_link); 167 err |= __put_user(0, &frame->rs_uc.uc_link);
168 sp = (int) (long) current->sas_ss_sp; 168 sp = (int) (long) current->sas_ss_sp;
169 err |= __put_user(sp, 169 err |= __put_user(sp,
170 &frame->rs_uc.uc_stack.ss_sp); 170 &frame->rs_uc.uc_stack.ss_sp);
171 err |= __put_user(sas_ss_flags(regs->regs[29]), 171 err |= __put_user(sas_ss_flags(regs->regs[29]),
172 &frame->rs_uc.uc_stack.ss_flags); 172 &frame->rs_uc.uc_stack.ss_flags);
173 err |= __put_user(current->sas_ss_size, 173 err |= __put_user(current->sas_ss_size,
174 &frame->rs_uc.uc_stack.ss_size); 174 &frame->rs_uc.uc_stack.ss_size);
175 err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext); 175 err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
176 err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set); 176 err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
177 177
@@ -207,7 +207,7 @@ give_sigsegv:
207} 207}
208 208
209struct mips_abi mips_abi_n32 = { 209struct mips_abi mips_abi_n32 = {
210 .setup_rt_frame = setup_rt_frame_n32, 210 .setup_rt_frame = setup_rt_frame_n32,
211 .rt_signal_return_offset = 211 .rt_signal_return_offset =
212 offsetof(struct mips_vdso, n32_rt_signal_trampoline), 212 offsetof(struct mips_vdso, n32_rt_signal_trampoline),
213 .restart = __NR_N32_restart_syscall 213 .restart = __NR_N32_restart_syscall
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 06cd0c610f44..c2e5d74739b4 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -172,7 +172,7 @@ void __init cmp_smp_setup(void)
172 if (amon_cpu_avail(i)) { 172 if (amon_cpu_avail(i)) {
173 set_cpu_possible(i, true); 173 set_cpu_possible(i, true);
174 __cpu_number_map[i] = ++ncpu; 174 __cpu_number_map[i] = ++ncpu;
175 __cpu_logical_map[ncpu] = i; 175 __cpu_logical_map[ncpu] = i;
176 } 176 }
177 } 177 }
178 178
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2defa2bbdaa7..bfede063d96a 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -71,7 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
71 /* Record this as available CPU */ 71 /* Record this as available CPU */
72 set_cpu_possible(tc, true); 72 set_cpu_possible(tc, true);
73 __cpu_number_map[tc] = ++ncpu; 73 __cpu_number_map[tc] = ++ncpu;
74 __cpu_logical_map[ncpu] = tc; 74 __cpu_logical_map[ncpu] = tc;
75 } 75 }
76 76
77 /* Disable multi-threading with TC's */ 77 /* Disable multi-threading with TC's */
@@ -215,7 +215,7 @@ static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
215 write_tc_gpr_gp((unsigned long)gp); 215 write_tc_gpr_gp((unsigned long)gp);
216 216
217 flush_icache_range((unsigned long)gp, 217 flush_icache_range((unsigned long)gp,
218 (unsigned long)(gp + sizeof(struct thread_info))); 218 (unsigned long)(gp + sizeof(struct thread_info)));
219 219
220 /* finally out of configuration and into chaos */ 220 /* finally out of configuration and into chaos */
221 clear_c0_mvpcontrol(MVPCONTROL_VPC); 221 clear_c0_mvpcontrol(MVPCONTROL_VPC);
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 20938a4cb52d..76016ac0a9c8 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -65,7 +65,7 @@ FEXPORT(__smtc_ipi_vector)
651: 651:
66 /* 66 /*
67 * The IPI sender has put some information on the anticipated 67 * The IPI sender has put some information on the anticipated
68 * kernel stack frame. If we were in user mode, this will be 68 * kernel stack frame. If we were in user mode, this will be
69 * built above the saved kernel SP. If we were already in the 69 * built above the saved kernel SP. If we were already in the
70 * kernel, it will be built above the current CPU SP. 70 * kernel, it will be built above the current CPU SP.
71 * 71 *
diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c
index 145771c0ed7a..aee7c8177b5d 100644
--- a/arch/mips/kernel/smtc-proc.c
+++ b/arch/mips/kernel/smtc-proc.c
@@ -35,7 +35,7 @@ static struct proc_dir_entry *smtc_stats;
35atomic_t smtc_fpu_recoveries; 35atomic_t smtc_fpu_recoveries;
36 36
37static int proc_read_smtc(char *page, char **start, off_t off, 37static int proc_read_smtc(char *page, char **start, off_t off,
38 int count, int *eof, void *data) 38 int count, int *eof, void *data)
39{ 39{
40 int totalen = 0; 40 int totalen = 0;
41 int len; 41 int len;
@@ -68,7 +68,7 @@ static int proc_read_smtc(char *page, char **start, off_t off,
68 page += len; 68 page += len;
69 } 69 }
70 len = sprintf(page, "%d Recoveries of \"stolen\" FPU\n", 70 len = sprintf(page, "%d Recoveries of \"stolen\" FPU\n",
71 atomic_read(&smtc_fpu_recoveries)); 71 atomic_read(&smtc_fpu_recoveries));
72 totalen += len; 72 totalen += len;
73 page += len; 73 page += len;
74 74
@@ -87,5 +87,5 @@ void init_smtc_stats(void)
87 atomic_set(&smtc_fpu_recoveries, 0); 87 atomic_set(&smtc_fpu_recoveries, 0);
88 88
89 smtc_stats = create_proc_read_entry("smtc", 0444, NULL, 89 smtc_stats = create_proc_read_entry("smtc", 0444, NULL,
90 proc_read_smtc, NULL); 90 proc_read_smtc, NULL);
91} 91}
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 1d47843d3cc0..1c152a93dc7b 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -235,7 +235,7 @@ static void smtc_configure_tlb(void)
235 mips_ihb(); 235 mips_ihb();
236 /* No need to un-Halt - that happens later anyway */ 236 /* No need to un-Halt - that happens later anyway */
237 for (i=0; i < vpes; i++) { 237 for (i=0; i < vpes; i++) {
238 write_tc_c0_tcbind(i); 238 write_tc_c0_tcbind(i);
239 /* 239 /*
240 * To be 100% sure we're really getting the right 240 * To be 100% sure we're really getting the right
241 * information, we exit the configuration state 241 * information, we exit the configuration state
@@ -286,7 +286,7 @@ static void smtc_configure_tlb(void)
286 286
287/* 287/*
288 * Incrementally build the CPU map out of constituent MIPS MT cores, 288 * Incrementally build the CPU map out of constituent MIPS MT cores,
289 * using the specified available VPEs and TCs. Plaform code needs 289 * using the specified available VPEs and TCs. Plaform code needs
290 * to ensure that each MIPS MT core invokes this routine on reset, 290 * to ensure that each MIPS MT core invokes this routine on reset,
291 * one at a time(!). 291 * one at a time(!).
292 * 292 *
@@ -348,7 +348,7 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
348 { 348 {
349 /* 349 /*
350 * FIXME: Multi-core SMTC hasn't been tested and the 350 * FIXME: Multi-core SMTC hasn't been tested and the
351 * maximum number of VPEs may change. 351 * maximum number of VPEs may change.
352 */ 352 */
353 cp1contexts[0] = smtc_nconf1[0] - 1; 353 cp1contexts[0] = smtc_nconf1[0] - 1;
354 cp1contexts[1] = smtc_nconf1[1]; 354 cp1contexts[1] = smtc_nconf1[1];
@@ -761,9 +761,9 @@ void smtc_forward_irq(struct irq_data *d)
761 * mask has been purged of bits corresponding to nonexistent and 761 * mask has been purged of bits corresponding to nonexistent and
762 * offline "CPUs", and to TCs bound to VPEs other than the VPE 762 * offline "CPUs", and to TCs bound to VPEs other than the VPE
763 * connected to the physical interrupt input for the interrupt 763 * connected to the physical interrupt input for the interrupt
764 * in question. Otherwise we have a nasty problem with interrupt 764 * in question. Otherwise we have a nasty problem with interrupt
765 * mask management. This is best handled in non-performance-critical 765 * mask management. This is best handled in non-performance-critical
766 * platform IRQ affinity setting code, to minimize interrupt-time 766 * platform IRQ affinity setting code, to minimize interrupt-time
767 * checks. 767 * checks.
768 */ 768 */
769 769
@@ -899,10 +899,10 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
899 mips_ihb(); 899 mips_ihb();
900 900
901 /* 901 /*
902 * Inspect TCStatus - if IXMT is set, we have to queue 902 * Inspect TCStatus - if IXMT is set, we have to queue
903 * a message. Otherwise, we set up the "interrupt" 903 * a message. Otherwise, we set up the "interrupt"
904 * of the other TC 904 * of the other TC
905 */ 905 */
906 tcstatus = read_tc_c0_tcstatus(); 906 tcstatus = read_tc_c0_tcstatus();
907 907
908 if ((tcstatus & TCSTATUS_IXMT) != 0) { 908 if ((tcstatus & TCSTATUS_IXMT) != 0) {
@@ -964,7 +964,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
964 * CU bit of Status is indicator that TC was 964 * CU bit of Status is indicator that TC was
965 * already running on a kernel stack... 965 * already running on a kernel stack...
966 */ 966 */
967 if (tcstatus & ST0_CU0) { 967 if (tcstatus & ST0_CU0) {
968 /* Note that this "- 1" is pointer arithmetic */ 968 /* Note that this "- 1" is pointer arithmetic */
969 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; 969 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
970 } else { 970 } else {
@@ -1288,7 +1288,7 @@ void smtc_idle_loop_hook(void)
1288 for (tc = 0; tc < hook_ntcs; tc++) { 1288 for (tc = 0; tc < hook_ntcs; tc++) {
1289 tcnoprog[tc] = 0; 1289 tcnoprog[tc] = 0;
1290 clock_hang_reported[tc] = 0; 1290 clock_hang_reported[tc] = 0;
1291 } 1291 }
1292 for (vpe = 0; vpe < 2; vpe++) 1292 for (vpe = 0; vpe < 2; vpe++)
1293 for (im = 0; im < 8; im++) 1293 for (im = 0; im < 8; im++)
1294 imstuckcount[vpe][im] = 0; 1294 imstuckcount[vpe][im] = 0;
@@ -1485,7 +1485,7 @@ static int halt_state_save[NR_CPUS];
1485 1485
1486/* 1486/*
1487 * To really, really be sure that nothing is being done 1487 * To really, really be sure that nothing is being done
1488 * by other TCs, halt them all. This code assumes that 1488 * by other TCs, halt them all. This code assumes that
1489 * a DVPE has already been done, so while their Halted 1489 * a DVPE has already been done, so while their Halted
1490 * state is theoretically architecturally unstable, in 1490 * state is theoretically architecturally unstable, in
1491 * practice, it's not going to change while we're looking 1491 * practice, it's not going to change while we're looking
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 7f1eca3858de..1ff43d5ac2c4 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -25,7 +25,7 @@ static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0);
25static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0); 25static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
26static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0); 26static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
27 27
28#define COUNTON 100 28#define COUNTON 100
29#define NR_LOOPS 5 29#define NR_LOOPS 5
30 30
31void __cpuinit synchronise_count_master(int cpu) 31void __cpuinit synchronise_count_master(int cpu)
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 107307d583eb..d7feee0c2739 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -41,9 +41,9 @@
41 41
42/* 42/*
43 * For historic reasons the pipe(2) syscall on MIPS has an unusual calling 43 * For historic reasons the pipe(2) syscall on MIPS has an unusual calling
44 * convention. It returns results in registers $v0 / $v1 which means there 44 * convention. It returns results in registers $v0 / $v1 which means there
45 * is no need for it to do verify the validity of a userspace pointer 45 * is no need for it to do verify the validity of a userspace pointer
46 * argument. Historically that used to be expensive in Linux. These days 46 * argument. Historically that used to be expensive in Linux. These days
47 * the performance advantage is negligible. 47 * the performance advantage is negligible.
48 */ 48 */
49asmlinkage int sysm_pipe(nabi_no_regargs volatile struct pt_regs regs) 49asmlinkage int sysm_pipe(nabi_no_regargs volatile struct pt_regs regs)
@@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs)
124 child_tidptr = (int __user *) regs.regs[8]; 124 child_tidptr = (int __user *) regs.regs[8];
125#endif 125#endif
126 return do_fork(clone_flags, newsp, 0, 126 return do_fork(clone_flags, newsp, 0,
127 parent_tidptr, child_tidptr); 127 parent_tidptr, child_tidptr);
128} 128}
129 129
130SYSCALL_DEFINE1(set_thread_area, unsigned long, addr) 130SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 99d73b72b00b..9d686bf97b0e 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -5,8 +5,8 @@
5 * 5 *
6 * Common time service routines for MIPS machines. 6 * Common time service routines for MIPS machines.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your 10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
@@ -62,8 +62,8 @@ EXPORT_SYMBOL(perf_irq);
62 * time_init() - it does the following things. 62 * time_init() - it does the following things.
63 * 63 *
64 * 1) plat_time_init() - 64 * 1) plat_time_init() -
65 * a) (optional) set up RTC routines, 65 * a) (optional) set up RTC routines,
66 * b) (optional) calibrate and set the mips_hpt_frequency 66 * b) (optional) calibrate and set the mips_hpt_frequency
67 * (only needed if you intended to use cpu counter as timer interrupt 67 * (only needed if you intended to use cpu counter as timer interrupt
68 * source) 68 * source)
69 * 2) calculate a couple of cached variables for later usage 69 * 2) calculate a couple of cached variables for later usage
@@ -75,7 +75,7 @@ unsigned int mips_hpt_frequency;
75 * This function exists in order to cause an error due to a duplicate 75 * This function exists in order to cause an error due to a duplicate
76 * definition if platform code should have its own implementation. The hook 76 * definition if platform code should have its own implementation. The hook
77 * to use instead is plat_time_init. plat_time_init does not receive the 77 * to use instead is plat_time_init. plat_time_init does not receive the
78 * irqaction pointer argument anymore. This is because any function which 78 * irqaction pointer argument anymore. This is because any function which
79 * initializes an interrupt timer now takes care of its own request_irq rsp. 79 * initializes an interrupt timer now takes care of its own request_irq rsp.
80 * setup_irq calls and each clock_event_device should use its own 80 * setup_irq calls and each clock_event_device should use its own
81 * struct irqrequest. 81 * struct irqrequest.
@@ -93,7 +93,7 @@ static __init int cpu_has_mfc0_count_bug(void)
93 case CPU_R4000MC: 93 case CPU_R4000MC:
94 /* 94 /*
95 * V3.0 is documented as suffering from the mfc0 from count bug. 95 * V3.0 is documented as suffering from the mfc0 from count bug.
96 * Afaik this is the last version of the R4000. Later versions 96 * Afaik this is the last version of the R4000. Later versions
97 * were marketed as R4400. 97 * were marketed as R4400.
98 */ 98 */
99 return 1; 99 return 1;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e3a5f3ddab1a..08c07bdb7e6c 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -164,7 +164,7 @@ static void show_stacktrace(struct task_struct *task,
164 i = 0; 164 i = 0;
165 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 165 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
166 if (i && ((i % (64 / field)) == 0)) 166 if (i && ((i % (64 / field)) == 0))
167 printk("\n "); 167 printk("\n ");
168 if (i > 39) { 168 if (i > 39) {
169 printk(" ..."); 169 printk(" ...");
170 break; 170 break;
@@ -279,7 +279,7 @@ static void __show_regs(const struct pt_regs *regs)
279 printk("ra : %0*lx %pS\n", field, regs->regs[31], 279 printk("ra : %0*lx %pS\n", field, regs->regs[31],
280 (void *) regs->regs[31]); 280 (void *) regs->regs[31]);
281 281
282 printk("Status: %08x ", (uint32_t) regs->cp0_status); 282 printk("Status: %08x ", (uint32_t) regs->cp0_status);
283 283
284 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 284 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
285 if (regs->cp0_status & ST0_KUO) 285 if (regs->cp0_status & ST0_KUO)
@@ -441,7 +441,7 @@ asmlinkage void do_be(struct pt_regs *regs)
441 int data = regs->cp0_cause & 4; 441 int data = regs->cp0_cause & 4;
442 int action = MIPS_BE_FATAL; 442 int action = MIPS_BE_FATAL;
443 443
444 /* XXX For now. Fixme, this searches the wrong table ... */ 444 /* XXX For now. Fixme, this searches the wrong table ... */
445 if (data && !user_mode(regs)) 445 if (data && !user_mode(regs))
446 fixup = search_dbe_tables(exception_epc(regs)); 446 fixup = search_dbe_tables(exception_epc(regs));
447 447
@@ -739,7 +739,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
739 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 739 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
740 740
741 /* Restore the hardware register state */ 741 /* Restore the hardware register state */
742 own_fpu(1); /* Using the FPU again. */ 742 own_fpu(1); /* Using the FPU again. */
743 743
744 /* If something went wrong, signal */ 744 /* If something went wrong, signal */
745 process_fpemu_return(sig, fault_addr); 745 process_fpemu_return(sig, fault_addr);
@@ -966,7 +966,7 @@ int cu2_notifier_call_chain(unsigned long val, void *v)
966} 966}
967 967
968static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 968static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
969 void *data) 969 void *data)
970{ 970{
971 struct pt_regs *regs = data; 971 struct pt_regs *regs = data;
972 972
@@ -974,7 +974,7 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
974 default: 974 default:
975 die_if_kernel("Unhandled kernel unaligned access or invalid " 975 die_if_kernel("Unhandled kernel unaligned access or invalid "
976 "instruction", regs); 976 "instruction", regs);
977 /* Fall through */ 977 /* Fall through */
978 978
979 case CU2_EXCEPTION: 979 case CU2_EXCEPTION:
980 force_sig(SIGILL, current); 980 force_sig(SIGILL, current);
@@ -1029,10 +1029,10 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1029 /* 1029 /*
1030 * Old (MIPS I and MIPS II) processors will set this code 1030 * Old (MIPS I and MIPS II) processors will set this code
1031 * for COP1X opcode instructions that replaced the original 1031 * for COP1X opcode instructions that replaced the original
1032 * COP3 space. We don't limit COP1 space instructions in 1032 * COP3 space. We don't limit COP1 space instructions in
1033 * the emulator according to the CPU ISA, so we want to 1033 * the emulator according to the CPU ISA, so we want to
1034 * treat COP1X instructions consistently regardless of which 1034 * treat COP1X instructions consistently regardless of which
1035 * code the CPU chose. Therefore we redirect this trap to 1035 * code the CPU chose. Therefore we redirect this trap to
1036 * the FP emulator too. 1036 * the FP emulator too.
1037 * 1037 *
1038 * Then some newer FPU-less processors use this code 1038 * Then some newer FPU-less processors use this code
@@ -1044,9 +1044,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1044 /* Fall through. */ 1044 /* Fall through. */
1045 1045
1046 case 1: 1046 case 1:
1047 if (used_math()) /* Using the FPU again. */ 1047 if (used_math()) /* Using the FPU again. */
1048 own_fpu(1); 1048 own_fpu(1);
1049 else { /* First time FPU user. */ 1049 else { /* First time FPU user. */
1050 init_fpu(); 1050 init_fpu();
1051 set_used_math(); 1051 set_used_math();
1052 } 1052 }
@@ -1114,7 +1114,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
1114 show_regs(regs); 1114 show_regs(regs);
1115 1115
1116 if (multi_match) { 1116 if (multi_match) {
1117 printk("Index : %0x\n", read_c0_index()); 1117 printk("Index : %0x\n", read_c0_index());
1118 printk("Pagemask: %0x\n", read_c0_pagemask()); 1118 printk("Pagemask: %0x\n", read_c0_pagemask());
1119 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1119 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1120 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1120 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
@@ -1181,7 +1181,7 @@ asmlinkage void do_dsp(struct pt_regs *regs)
1181asmlinkage void do_reserved(struct pt_regs *regs) 1181asmlinkage void do_reserved(struct pt_regs *regs)
1182{ 1182{
1183 /* 1183 /*
1184 * Game over - no way to handle this if it ever occurs. Most probably 1184 * Game over - no way to handle this if it ever occurs. Most probably
1185 * caused by a new unknown cpu type or after another deadly 1185 * caused by a new unknown cpu type or after another deadly
1186 * hard/software error. 1186 * hard/software error.
1187 */ 1187 */
@@ -1705,7 +1705,7 @@ void __init trap_init(void)
1705 1705
1706#if defined(CONFIG_KGDB) 1706#if defined(CONFIG_KGDB)
1707 if (kgdb_early_setup) 1707 if (kgdb_early_setup)
1708 return; /* Already done */ 1708 return; /* Already done */
1709#endif 1709#endif
1710 1710
1711 if (cpu_has_veic || cpu_has_vint) { 1711 if (cpu_has_veic || cpu_has_vint) {
@@ -1799,7 +1799,7 @@ void __init trap_init(void)
1799 * The R6000 is the only R-series CPU that features a machine 1799 * The R6000 is the only R-series CPU that features a machine
1800 * check exception (similar to the R4000 cache error) and 1800 * check exception (similar to the R4000 cache error) and
1801 * unaligned ldc1/sdc1 exception. The handlers have not been 1801 * unaligned ldc1/sdc1 exception. The handlers have not been
1802 * written yet. Well, anyway there is no R6000 machine on the 1802 * written yet. Well, anyway there is no R6000 machine on the
1803 * current list of targets for Linux/MIPS. 1803 * current list of targets for Linux/MIPS.
1804 * (Duh, crap, there is someone with a triple R6k machine) 1804 * (Duh, crap, there is someone with a triple R6k machine)
1805 */ 1805 */
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 9c58bdf58f23..6087a54c86a0 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -21,11 +21,11 @@
21 * 21 *
22 * For now I enable fixing of address errors by default to make life easier. 22 * For now I enable fixing of address errors by default to make life easier.
23 * I however intend to disable this somewhen in the future when the alignment 23 * I however intend to disable this somewhen in the future when the alignment
24 * problems with user programs have been fixed. For programmers this is the 24 * problems with user programs have been fixed. For programmers this is the
25 * right way to go. 25 * right way to go.
26 * 26 *
27 * Fixing address errors is a per process option. The option is inherited 27 * Fixing address errors is a per process option. The option is inherited
28 * across fork(2) and execve(2) calls. If you really want to use the 28 * across fork(2) and execve(2) calls. If you really want to use the
29 * option in your user programs - I discourage the use of the software 29 * option in your user programs - I discourage the use of the software
30 * emulation strongly - use the following code in your userland stuff: 30 * emulation strongly - use the following code in your userland stuff:
31 * 31 *
@@ -43,34 +43,34 @@
43 * #include <sys/sysmips.h> 43 * #include <sys/sysmips.h>
44 * 44 *
45 * struct foo { 45 * struct foo {
46 * unsigned char bar[8]; 46 * unsigned char bar[8];
47 * }; 47 * };
48 * 48 *
49 * main(int argc, char *argv[]) 49 * main(int argc, char *argv[])
50 * { 50 * {
51 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7}; 51 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
52 * unsigned int *p = (unsigned int *) (x.bar + 3); 52 * unsigned int *p = (unsigned int *) (x.bar + 3);
53 * int i; 53 * int i;
54 * 54 *
55 * if (argc > 1) 55 * if (argc > 1)
56 * sysmips(MIPS_FIXADE, atoi(argv[1])); 56 * sysmips(MIPS_FIXADE, atoi(argv[1]));
57 * 57 *
58 * printf("*p = %08lx\n", *p); 58 * printf("*p = %08lx\n", *p);
59 * 59 *
60 * *p = 0xdeadface; 60 * *p = 0xdeadface;
61 * 61 *
62 * for(i = 0; i <= 7; i++) 62 * for(i = 0; i <= 7; i++)
63 * printf("%02x ", x.bar[i]); 63 * printf("%02x ", x.bar[i]);
64 * printf("\n"); 64 * printf("\n");
65 * } 65 * }
66 * 66 *
67 * Coprocessor loads are not supported; I think this case is unimportant 67 * Coprocessor loads are not supported; I think this case is unimportant
68 * in the practice. 68 * in the practice.
69 * 69 *
70 * TODO: Handle ndc (attempted store to doubleword in uncached memory) 70 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
71 * exception for the R6000. 71 * exception for the R6000.
72 * A store crossing a page boundary might be executed only partially. 72 * A store crossing a page boundary might be executed only partially.
73 * Undo the partial store in this case. 73 * Undo the partial store in this case.
74 */ 74 */
75#include <linux/mm.h> 75#include <linux/mm.h>
76#include <linux/signal.h> 76#include <linux/signal.h>
@@ -86,7 +86,7 @@
86#include <asm/inst.h> 86#include <asm/inst.h>
87#include <asm/uaccess.h> 87#include <asm/uaccess.h>
88 88
89#define STR(x) __STR(x) 89#define STR(x) __STR(x)
90#define __STR(x) #x 90#define __STR(x) #x
91 91
92enum { 92enum {
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 0a4336b803e9..05826d20a792 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -22,12 +22,12 @@ PHDRS {
22 22
23#ifdef CONFIG_32BIT 23#ifdef CONFIG_32BIT
24 #ifdef CONFIG_CPU_LITTLE_ENDIAN 24 #ifdef CONFIG_CPU_LITTLE_ENDIAN
25 jiffies = jiffies_64; 25 jiffies = jiffies_64;
26 #else 26 #else
27 jiffies = jiffies_64 + 4; 27 jiffies = jiffies_64 + 4;
28 #endif 28 #endif
29#else 29#else
30 jiffies = jiffies_64; 30 jiffies = jiffies_64;
31#endif 31#endif
32 32
33SECTIONS 33SECTIONS
@@ -139,7 +139,7 @@ SECTIONS
139 139
140 /* 140 /*
141 * Force .bss to 64K alignment so that .bss..swapper_pg_dir 141 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
142 * gets that alignment. .sbss should be empty, so there will be 142 * gets that alignment. .sbss should be empty, so there will be
143 * no holes after __init_end. */ 143 * no holes after __init_end. */
144 BSS_SECTION(0, 0x10000, 0) 144 BSS_SECTION(0, 0x10000, 0)
145 145
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 147cec19621d..32fc5d4a22e5 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -254,7 +254,7 @@ static void __maybe_unused dump_mtregs(void)
254 val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); 254 val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
255} 255}
256 256
257/* Find some VPE program space */ 257/* Find some VPE program space */
258static void *alloc_progmem(unsigned long len) 258static void *alloc_progmem(unsigned long len)
259{ 259{
260 void *addr; 260 void *addr;
@@ -292,7 +292,7 @@ static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
292} 292}
293 293
294/* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld 294/* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld
295 might -- code, read-only data, read-write data, small data. Tally 295 might -- code, read-only data, read-write data, small data. Tally
296 sizes, and place the offsets into sh_entsize fields: high bit means it 296 sizes, and place the offsets into sh_entsize fields: high bit means it
297 belongs in init. */ 297 belongs in init. */
298static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, 298static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
@@ -386,7 +386,7 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location,
386 386
387 if( (rel > 32768) || (rel < -32768) ) { 387 if( (rel > 32768) || (rel < -32768) ) {
388 printk(KERN_DEBUG "VPE loader: " 388 printk(KERN_DEBUG "VPE loader: "
389 "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); 389 "apply_r_mips_pc16: relative address out of range 0x%x\n", rel);
390 return -ENOEXEC; 390 return -ENOEXEC;
391 } 391 }
392 392
@@ -458,7 +458,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
458 Elf32_Addr val, vallo; 458 Elf32_Addr val, vallo;
459 struct mips_hi16 *l, *next; 459 struct mips_hi16 *l, *next;
460 460
461 /* Sign extend the addend we extract from the lo insn. */ 461 /* Sign extend the addend we extract from the lo insn. */
462 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; 462 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
463 463
464 if (mips_hi16_list != NULL) { 464 if (mips_hi16_list != NULL) {
@@ -470,7 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
470 /* 470 /*
471 * The value for the HI16 had best be the same. 471 * The value for the HI16 had best be the same.
472 */ 472 */
473 if (v != l->value) { 473 if (v != l->value) {
474 printk(KERN_DEBUG "VPE loader: " 474 printk(KERN_DEBUG "VPE loader: "
475 "apply_r_mips_lo16/hi16: \t" 475 "apply_r_mips_lo16/hi16: \t"
476 "inconsistent value information\n"); 476 "inconsistent value information\n");
@@ -505,7 +505,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
505 } 505 }
506 506
507 /* 507 /*
508 * Ok, we're done with the HI16 relocs. Now deal with the LO16. 508 * Ok, we're done with the HI16 relocs. Now deal with the LO16.
509 */ 509 */
510 val = v + vallo; 510 val = v + vallo;
511 insnlo = (insnlo & ~0xffff) | (val & 0xffff); 511 insnlo = (insnlo & ~0xffff) | (val & 0xffff);
@@ -579,7 +579,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs,
579 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); 579 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
580 if( res ) { 580 if( res ) {
581 char *r = rstrs[ELF32_R_TYPE(r_info)]; 581 char *r = rstrs[ELF32_R_TYPE(r_info)];
582 printk(KERN_WARNING "VPE loader: .text+0x%x " 582 printk(KERN_WARNING "VPE loader: .text+0x%x "
583 "relocation type %s for symbol \"%s\" failed\n", 583 "relocation type %s for symbol \"%s\" failed\n",
584 rel[i].r_offset, r ? r : "UNKNOWN", 584 rel[i].r_offset, r ? r : "UNKNOWN",
585 strtab + sym->st_name); 585 strtab + sym->st_name);
@@ -772,7 +772,7 @@ static int vpe_run(struct vpe * v)
772 772
773 /* Set up the XTC bit in vpeconf0 to point at our tc */ 773 /* Set up the XTC bit in vpeconf0 to point at our tc */
774 write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) 774 write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
775 | (t->index << VPECONF0_XTC_SHIFT)); 775 | (t->index << VPECONF0_XTC_SHIFT));
776 776
777 back_to_back_c0_hazard(); 777 back_to_back_c0_hazard();
778 778
@@ -926,34 +926,34 @@ static int vpe_elfload(struct vpe * v)
926 secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); 926 secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr);
927 } 927 }
928 928
929 /* Fix up syms, so that st_value is a pointer to location. */ 929 /* Fix up syms, so that st_value is a pointer to location. */
930 simplify_symbols(sechdrs, symindex, strtab, secstrings, 930 simplify_symbols(sechdrs, symindex, strtab, secstrings,
931 hdr->e_shnum, &mod); 931 hdr->e_shnum, &mod);
932 932
933 /* Now do relocations. */ 933 /* Now do relocations. */
934 for (i = 1; i < hdr->e_shnum; i++) { 934 for (i = 1; i < hdr->e_shnum; i++) {
935 const char *strtab = (char *)sechdrs[strindex].sh_addr; 935 const char *strtab = (char *)sechdrs[strindex].sh_addr;
936 unsigned int info = sechdrs[i].sh_info; 936 unsigned int info = sechdrs[i].sh_info;
937 937
938 /* Not a valid relocation section? */ 938 /* Not a valid relocation section? */
939 if (info >= hdr->e_shnum) 939 if (info >= hdr->e_shnum)
940 continue; 940 continue;
941 941
942 /* Don't bother with non-allocated sections */ 942 /* Don't bother with non-allocated sections */
943 if (!(sechdrs[info].sh_flags & SHF_ALLOC)) 943 if (!(sechdrs[info].sh_flags & SHF_ALLOC))
944 continue; 944 continue;
945 945
946 if (sechdrs[i].sh_type == SHT_REL) 946 if (sechdrs[i].sh_type == SHT_REL)
947 err = apply_relocations(sechdrs, strtab, symindex, i, 947 err = apply_relocations(sechdrs, strtab, symindex, i,
948 &mod); 948 &mod);
949 else if (sechdrs[i].sh_type == SHT_RELA) 949 else if (sechdrs[i].sh_type == SHT_RELA)
950 err = apply_relocate_add(sechdrs, strtab, symindex, i, 950 err = apply_relocate_add(sechdrs, strtab, symindex, i,
951 &mod); 951 &mod);
952 if (err < 0) 952 if (err < 0)
953 return err; 953 return err;
954 954
955 } 955 }
956 } else { 956 } else {
957 struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); 957 struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
958 958
959 for (i = 0; i < hdr->e_phnum; i++) { 959 for (i = 0; i < hdr->e_phnum; i++) {
@@ -968,16 +968,16 @@ static int vpe_elfload(struct vpe * v)
968 } 968 }
969 969
970 for (i = 0; i < hdr->e_shnum; i++) { 970 for (i = 0; i < hdr->e_shnum; i++) {
971 /* Internal symbols and strings. */ 971 /* Internal symbols and strings. */
972 if (sechdrs[i].sh_type == SHT_SYMTAB) { 972 if (sechdrs[i].sh_type == SHT_SYMTAB) {
973 symindex = i; 973 symindex = i;
974 strindex = sechdrs[i].sh_link; 974 strindex = sechdrs[i].sh_link;
975 strtab = (char *)hdr + sechdrs[strindex].sh_offset; 975 strtab = (char *)hdr + sechdrs[strindex].sh_offset;
976 976
977 /* mark the symtab's address for when we try to find the 977 /* mark the symtab's address for when we try to find the
978 magic symbols */ 978 magic symbols */
979 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 979 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
980 } 980 }
981 } 981 }
982 } 982 }
983 983
@@ -1049,7 +1049,7 @@ static int getcwd(char *buff, int size)
1049 return ret; 1049 return ret;
1050} 1050}
1051 1051
1052/* checks VPE is unused and gets ready to load program */ 1052/* checks VPE is unused and gets ready to load program */
1053static int vpe_open(struct inode *inode, struct file *filp) 1053static int vpe_open(struct inode *inode, struct file *filp)
1054{ 1054{
1055 enum vpe_state state; 1055 enum vpe_state state;
@@ -1121,11 +1121,11 @@ static int vpe_release(struct inode *inode, struct file *filp)
1121 if (vpe_elfload(v) >= 0) { 1121 if (vpe_elfload(v) >= 0) {
1122 vpe_run(v); 1122 vpe_run(v);
1123 } else { 1123 } else {
1124 printk(KERN_WARNING "VPE loader: ELF load failed.\n"); 1124 printk(KERN_WARNING "VPE loader: ELF load failed.\n");
1125 ret = -ENOEXEC; 1125 ret = -ENOEXEC;
1126 } 1126 }
1127 } else { 1127 } else {
1128 printk(KERN_WARNING "VPE loader: only elf files are supported\n"); 1128 printk(KERN_WARNING "VPE loader: only elf files are supported\n");
1129 ret = -ENOEXEC; 1129 ret = -ENOEXEC;
1130 } 1130 }
1131 1131
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index c15406968030..7726f6157d9e 100644
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -12,7 +12,7 @@
12#include <asm/watch.h> 12#include <asm/watch.h>
13 13
14/* 14/*
15 * Install the watch registers for the current thread. A maximum of 15 * Install the watch registers for the current thread. A maximum of
16 * four registers are installed although the machine may have more. 16 * four registers are installed although the machine may have more.
17 */ 17 */
18void mips_install_watch_registers(void) 18void mips_install_watch_registers(void)
@@ -72,7 +72,7 @@ void mips_read_watch_registers(void)
72 } 72 }
73 73
74/* 74/*
75 * Disable all watch registers. Although only four registers are 75 * Disable all watch registers. Although only four registers are
76 * installed, all are cleared to eliminate the possibility of endless 76 * installed, all are cleared to eliminate the possibility of endless
77 * looping in the watch handler. 77 * looping in the watch handler.
78 */ 78 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 06:02:07 -0500