11 files changed, 149 insertions, 128 deletions

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index c6136cb4cd40..d6c2a7476bac 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -34,28 +34,11 @@ obj-$(CONFIG_MODULES)		+= mips_ksyms.o module.o
 
 obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o ftrace.o
 
-obj-$(CONFIG_CPU_LOONGSON2)     += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_MIPS32)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_MIPS64)        += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4K_FPU)       += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R3000)         += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_R4300)         += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R4X00)         += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R5000)         += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R6000)         += r6000_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R5432)         += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R5500)         += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R8000)         += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_RM7000)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_RM9000)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_NEVADA)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R10000)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_SB1)           += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_TX39XX)        += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_TX49XX)        += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_VR41XX)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
-obj-$(CONFIG_CPU_XLR)           += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_XLP)           += r4k_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SMP_UP)            += smp-up.o
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9599d..75323925e537 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,7 @@
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
+#include <asm/gic.h>
 
 /*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
@@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev)
  */
 static int c0_compare_int_pending(void)
 {
+#ifdef CONFIG_IRQ_GIC
+        if (cpu_has_veic)
+                return gic_get_timer_pending();
+#endif
         return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
 }
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1b51046191e8..bc58bd10a607 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -421,8 +421,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 
         config3 = read_c0_config3();
 
-        if (config3 & MIPS_CONF3_SM)
+        if (config3 & MIPS_CONF3_SM) {
                 c->ases |= MIPS_ASE_SMARTMIPS;
+                c->options |= MIPS_CPU_RIXI;
+        }
+        if (config3 & MIPS_CONF3_RXI)
+                c->options |= MIPS_CPU_RIXI;
         if (config3 & MIPS_CONF3_DSP)
                 c->ases |= MIPS_ASE_DSP;
         if (config3 & MIPS_CONF3_VINT)
@@ -857,6 +861,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_1004K;
                 __cpu_name[cpu] = "MIPS 1004Kc";
                 break;
+        case PRID_IMP_1074K:
+                c->cputype = CPU_74K;
+                __cpu_name[cpu] = "MIPS 1074Kc";
+                break;
         }
 
         spram_config();
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 37acfa036d44..a6c133212003 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -77,7 +77,7 @@ FEXPORT(syscall_exit)
         and     t0, a2, t0
         bnez    t0, syscall_exit_work
 
-FEXPORT(restore_all)                    # restore full frame
+restore_all:                            # restore full frame
 #ifdef CONFIG_MIPS_MT_SMTC
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 /* Re-arm any temporarily masked interrupts not explicitly "acked" */
@@ -117,7 +117,7 @@ FEXPORT(restore_all)			# restore full frame
         RESTORE_TEMP
         RESTORE_AT
         RESTORE_STATIC
-FEXPORT(restore_partial)                # restore partial frame
+restore_partial:                # restore partial frame
 #ifdef CONFIG_TRACE_IRQFLAGS
         SAVE_STATIC
         SAVE_AT
@@ -164,9 +164,18 @@ work_notifysig:				# deal with pending signals and
         jal     do_notify_resume        # a2 already loaded
         j       resume_userspace
 
-FEXPORT(syscall_exit_work_partial)
+FEXPORT(syscall_exit_partial)
+        local_irq_disable               # make sure need_resched doesn't
+                                        # change between and return
+        LONG_L  a2, TI_FLAGS($28)       # current->work
+        li      t0, _TIF_ALLWORK_MASK
+        and     t0, a2
+        beqz    t0, restore_partial
         SAVE_STATIC
 syscall_exit_work:
+        LONG_L  t0, PT_STATUS(sp)               # returning to kernel mode?
+        andi    t0, t0, KU_USER
+        beqz    t0, resume_kernel
         li      t0, _TIF_WORK_SYSCALL_EXIT
         and     t0, a2                  # a2 is preloaded with TI_FLAGS
         beqz    t0, work_pending        # trace bit set?
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 0c527f652196..485e6a961b31 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -1,5 +1,11 @@
-#undef DEBUG
-
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
+ */
 #include <linux/bitmap.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -7,33 +13,80 @@
 
 #include <asm/io.h>
 #include <asm/gic.h>
+#include <asm/setup.h>
+#include <asm/traps.h>
 #include <asm/gcmpregs.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
 
+unsigned long _gic_base;
+unsigned int gic_irq_base;
+unsigned int gic_irq_flags[GIC_NUM_INTRS];
 
-static unsigned long _gic_base;
-static unsigned int _irqbase;
-static unsigned int gic_irq_flags[GIC_NUM_INTRS];
-#define GIC_IRQ_FLAG_EDGE      0x0001
+/* The index into this array is the vector # of the interrupt. */
+struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
 
-struct gic_pcpu_mask pcpu_masks[NR_CPUS];
+static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
 
+unsigned int gic_get_timer_pending(void)
+{
+        unsigned int vpe_pending;
+
+        GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
+        GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
+        return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
+}
+
+void gic_bind_eic_interrupt(int irq, int set)
+{
+        /* Convert irq vector # to hw int # */
+        irq -= GIC_PIN_TO_VEC_OFFSET;
+
+        /* Set irq to use shadow set */
+        GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
+}
+
 void gic_send_ipi(unsigned int intr)
 {
-        pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
-                 read_c0_status());
         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 }
 
-/* This is Malta specific and needs to be exported */
+static void gic_eic_irq_dispatch(void)
+{
+        unsigned int cause = read_c0_cause();
+        int irq;
+
+        irq = (cause & ST0_IM) >> STATUSB_IP2;
+        if (irq == 0)
+                irq = -1;
+
+        if (irq >= 0)
+                do_IRQ(gic_irq_base + irq);
+        else
+                spurious_interrupt();
+}
+
 static void __init vpe_local_setup(unsigned int numvpes)
 {
-        int i;
-        unsigned long timer_interrupt = 5, perf_interrupt = 5;
+        unsigned long timer_intr = GIC_INT_TMR;
+        unsigned long perf_intr = GIC_INT_PERFCTR;
         unsigned int vpe_ctl;
+        int i;
+
+        if (cpu_has_veic) {
+                /*
+                 * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+                /*
+                 * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+        }
 
         /*
          * Setup the default performance counter timer interrupts
@@ -46,11 +99,20 @@ static void __init vpe_local_setup(unsigned int numvpes)
                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
-                                 GIC_MAP_TO_PIN_MSK | timer_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | timer_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
+                }
 
                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
-                                 GIC_MAP_TO_PIN_MSK | perf_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | perf_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
+                        gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
+                }
         }
 }
 
@@ -80,51 +142,30 @@ unsigned int gic_get_int(void)
         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 
-        i = find_first_bit(pending, GIC_NUM_INTRS);
-
-        pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
-
-        return i;
-}
-
-static void gic_irq_ack(struct irq_data *d)
-{
-        unsigned int irq = d->irq - _irqbase;
-
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_CLR_INTR_MASK(irq);
-
-        if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
-                GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
+        return find_first_bit(pending, GIC_NUM_INTRS);
 }
 
 static void gic_mask_irq(struct irq_data *d)
 {
-        unsigned int irq = d->irq - _irqbase;
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_CLR_INTR_MASK(irq);
+        GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
-        unsigned int irq = d->irq - _irqbase;
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_SET_INTR_MASK(irq);
+        GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 }
 
 #ifdef CONFIG_SMP
-
 static DEFINE_SPINLOCK(gic_lock);
 
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
                             bool force)
 {
-        unsigned int irq = d->irq - _irqbase;
+        unsigned int irq = (d->irq - gic_irq_base);
         cpumask_t       tmp = CPU_MASK_NONE;
         unsigned long   flags;
         int             i;
 
-        pr_debug("%s(%d) called\n", __func__, irq);
         cpumask_and(&tmp, cpumask, cpu_online_mask);
         if (cpus_empty(tmp))
                 return -1;
@@ -154,7 +195,7 @@ static struct irq_chip gic_irq_controller = {
         .irq_mask               =       gic_mask_irq,
         .irq_mask_ack           =       gic_mask_irq,
         .irq_unmask             =       gic_unmask_irq,
-        .irq_eoi                =       gic_unmask_irq,
+        .irq_eoi                =       gic_finish_irq,
 #ifdef CONFIG_SMP
         .irq_set_affinity       =       gic_set_affinity,
 #endif
@@ -164,6 +205,8 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
         unsigned int pin, unsigned int polarity, unsigned int trigtype,
         unsigned int flags)
 {
+        struct gic_shared_intr_map *map_ptr;
+
         /* Setup Intr to Pin mapping */
         if (pin & GIC_MAP_TO_NMI_MSK) {
                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
@@ -178,6 +221,14 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
                          GIC_MAP_TO_PIN_MSK | pin);
                 /* Setup Intr to CPU mapping */
                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
+                if (cpu_has_veic) {
+                        set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
+                        if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
+                                BUG();
+                        map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
+                }
         }
 
         /* Setup Intr Polarity */
@@ -191,26 +242,39 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
         /* Initialise per-cpu Interrupt software masks */
         if (flags & GIC_FLAG_IPI)
                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
-        if (flags & GIC_FLAG_TRANSPARENT)
+        if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
                 GIC_SET_INTR_MASK(intr);
         if (trigtype == GIC_TRIG_EDGE)
-                gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
+                gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 }
 
 static void __init gic_basic_init(int numintrs, int numvpes,
                         struct gic_intr_map *intrmap, int mapsize)
 {
         unsigned int i, cpu;
+        unsigned int pin_offset = 0;
+
+        board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 
         /* Setup defaults */
         for (i = 0; i < numintrs; i++) {
                 GIC_SET_POLARITY(i, GIC_POL_POS);
                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
                 GIC_CLR_INTR_MASK(i);
-                if (i < GIC_NUM_INTRS)
+                if (i < GIC_NUM_INTRS) {
                         gic_irq_flags[i] = 0;
+                        gic_shared_intr_map[i].num_shared_intr = 0;
+                        gic_shared_intr_map[i].local_intr_mask = 0;
+                }
         }
 
+        /*
+         * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
+         * one because the GIC will add one (since 0=no intr).
+         */
+        if (cpu_has_veic)
+                pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+
         /* Setup specifics */
         for (i = 0; i < mapsize; i++) {
                 cpu = intrmap[i].cpunum;
@@ -220,16 +284,13 @@ static void __init gic_basic_init(int numintrs, int numvpes,
                         continue;
                 gic_setup_intr(i,
                         intrmap[i].cpunum,
-                        intrmap[i].pin,
+                        intrmap[i].pin + pin_offset,
                         intrmap[i].polarity,
                         intrmap[i].trigtype,
                         intrmap[i].flags);
         }
 
         vpe_local_setup(numvpes);
-
-        for (i = _irqbase; i < (_irqbase + numintrs); i++)
-                irq_set_chip(i, &gic_irq_controller);
 }
 
 void __init gic_init(unsigned long gic_base_addr,
@@ -242,7 +303,7 @@ void __init gic_init(unsigned long gic_base_addr,
 
         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
                                                     gic_addrspace_size);
-        _irqbase = irqbase;
+        gic_irq_base = irqbase;
 
         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -251,8 +312,9 @@ void __init gic_init(unsigned long gic_base_addr,
 
         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
                   GIC_SH_CONFIG_NUMVPES_SHF;
-
-        pr_debug("%s called\n", __func__);
+        numvpes = numvpes + 1;
 
         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
+
+        gic_platform_init(numintrs, &gic_irq_controller);
 }
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index a632bc144efa..374f66e05f3d 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -69,18 +69,7 @@ stack_done:
 1:      sw      v0, PT_R2(sp)           # result
 
 o32_syscall_exit:
-        local_irq_disable               # make sure need_resched and
-                                        # signals dont change between
-                                        # sampling and return
-        lw      a2, TI_FLAGS($28)       # current->work
-        li      t0, _TIF_ALLWORK_MASK
-        and     t0, a2
-        bnez    t0, o32_syscall_exit_work
-
-        j       restore_partial
-
-o32_syscall_exit_work:
-        j       syscall_exit_work_partial
+        j       syscall_exit_partial
 
 /* ------------------------------------------------------------------------ */
 
@@ -593,6 +582,7 @@ einval:	li	v0, -ENOSYS
         sys     sys_setns               2
         sys     sys_process_vm_readv    6       /* 4345 */
         sys     sys_process_vm_writev   6
+        sys     sys_kcmp                5
         .endm
 
         /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3b5a5e9ae49c..169de6a6d916 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -72,18 +72,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
 1:      sd      v0, PT_R2(sp)           # result
 
 n64_syscall_exit:
-        local_irq_disable               # make sure need_resched and
-                                        # signals dont change between
-                                        # sampling and return
-        LONG_L  a2, TI_FLAGS($28)       # current->work
-        li      t0, _TIF_ALLWORK_MASK
-        and     t0, a2, t0
-        bnez    t0, n64_syscall_exit_work
-
-        j       restore_partial
-
-n64_syscall_exit_work:
-        j       syscall_exit_work_partial
+        j       syscall_exit_partial
 
 /* ------------------------------------------------------------------------ */
 
@@ -432,4 +421,5 @@ sys_call_table:
         PTR     sys_setns
         PTR     sys_process_vm_readv
         PTR     sys_process_vm_writev           /* 5305 */
+        PTR     sys_kcmp
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 6be6f7020923..f6ba8381ee01 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -70,18 +70,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
         sd      t1, PT_R0(sp)           # save it for syscall restarting
 1:      sd      v0, PT_R2(sp)           # result
 
-        local_irq_disable               # make sure need_resched and
-                                        # signals dont change between
-                                        # sampling and return
-        LONG_L  a2, TI_FLAGS($28)       # current->work
-        li      t0, _TIF_ALLWORK_MASK
-        and     t0, a2, t0
-        bnez    t0, n32_syscall_exit_work
-
-        j       restore_partial
-
-n32_syscall_exit_work:
-        j       syscall_exit_work_partial
+        j       syscall_exit_partial
 
 /* ------------------------------------------------------------------------ */
 
@@ -432,4 +421,5 @@ EXPORT(sysn32_call_table)
         PTR     sys_setns
         PTR     compat_sys_process_vm_readv
         PTR     compat_sys_process_vm_writev    /* 6310 */
+        PTR     sys_kcmp
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 54228553691d..53c2d7245764 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -99,18 +99,7 @@ NESTED(handle_sys, PT_SIZE, sp)
 1:      sd      v0, PT_R2(sp)           # result
 
 o32_syscall_exit:
-        local_irq_disable               # make need_resched and
-                                        # signals dont change between
-                                        # sampling and return
-        LONG_L  a2, TI_FLAGS($28)
-        li      t0, _TIF_ALLWORK_MASK
-        and     t0, a2, t0
-        bnez    t0, o32_syscall_exit_work
-
-        j       restore_partial
-
-o32_syscall_exit_work:
-        j       syscall_exit_work_partial
+        j       syscall_exit_partial
 
 /* ------------------------------------------------------------------------ */
 
@@ -550,4 +539,5 @@ sys_call_table:
         PTR     sys_setns
         PTR     compat_sys_process_vm_readv     /* 4345 */
         PTR     compat_sys_process_vm_writev
+        PTR     sys_kcmp
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index f2c09cfc60ac..0e1a5b8ae817 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -560,14 +560,6 @@ static void do_signal(struct pt_regs *regs)
         siginfo_t info;
         int signr;
 
-        /*
-         * We want the common case to go fast, which is why we may in certain
-         * cases get here from kernel mode. Just return without doing anything
-         * if so.
-         */
-        if (!user_mode(regs))
-                return;
-
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
                 /* Whee!  Actually deliver the signal.  */
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index ff17868734cf..2defa2bbdaa7 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -150,6 +150,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 
 static void __cpuinit vsmp_init_secondary(void)
 {
+#ifdef CONFIG_IRQ_GIC
         extern int gic_present;
 
         /* This is Malta specific: IPI,performance and timer interrupts */
@@ -157,6 +158,7 @@ static void __cpuinit vsmp_init_secondary(void)
                 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
                                          STATUSF_IP6 | STATUSF_IP7);
         else
+#endif
                 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
                                          STATUSF_IP6 | STATUSF_IP7);
 }