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-rw-r--r--arch/mips/kernel/irq-msc01.c6
-rw-r--r--arch/mips/kernel/irq_cpu.c3
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 963c16d266ab..6a8cd28133d5 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
140 140
141 switch (imp->im_type) { 141 switch (imp->im_type) {
142 case MSC01_IRQ_EDGE: 142 case MSC01_IRQ_EDGE:
143 set_irq_chip(irqbase+n, &msc_edgeirq_type); 143 set_irq_chip_and_handler_name(irqbase + n,
144 &msc_edgeirq_type, handle_edge_irq, "edge");
144 if (cpu_has_veic) 145 if (cpu_has_veic)
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 146 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
146 else 147 else
147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 148 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
148 break; 149 break;
149 case MSC01_IRQ_LEVEL: 150 case MSC01_IRQ_LEVEL:
150 set_irq_chip(irqbase+n, &msc_levelirq_type); 151 set_irq_chip_and_handler_name(irqbase+n,
152 &msc_levelirq_type, handle_level_irq, "level");
151 if (cpu_has_veic) 153 if (cpu_has_veic)
152 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 154 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
153 else 155 else
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0ee2567b780d..55c8a3ca507b 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
112 */ 112 */
113 if (cpu_has_mipsmt) 113 if (cpu_has_mipsmt)
114 for (i = irq_base; i < irq_base + 2; i++) 114 for (i = irq_base; i < irq_base + 2; i++)
115 set_irq_chip(i, &mips_mt_cpu_irq_controller); 115 set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
116 handle_percpu_irq);
116 117
117 for (i = irq_base + 2; i < irq_base + 8; i++) 118 for (i = irq_base + 2; i < irq_base + 8; i++)
118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 119 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,