diff options
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/early_printk.c | 11 | ||||
| -rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 | ||||
| -rw-r--r-- | arch/mips/kernel/irq.c | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/time.c | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 8 |
5 files changed, 21 insertions, 14 deletions
diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c index 4fa54b230c09..9dccfa4752b2 100644 --- a/arch/mips/kernel/early_printk.c +++ b/arch/mips/kernel/early_printk.c | |||
| @@ -12,7 +12,8 @@ | |||
| 12 | 12 | ||
| 13 | extern void prom_putchar(char); | 13 | extern void prom_putchar(char); |
| 14 | 14 | ||
| 15 | static void early_console_write(struct console *con, const char *s, unsigned n) | 15 | static void __init |
| 16 | early_console_write(struct console *con, const char *s, unsigned n) | ||
| 16 | { | 17 | { |
| 17 | while (n-- && *s) { | 18 | while (n-- && *s) { |
| 18 | if (*s == '\n') | 19 | if (*s == '\n') |
| @@ -22,14 +23,20 @@ static void early_console_write(struct console *con, const char *s, unsigned n) | |||
| 22 | } | 23 | } |
| 23 | } | 24 | } |
| 24 | 25 | ||
| 25 | static struct console early_console = { | 26 | static struct console early_console __initdata = { |
| 26 | .name = "early", | 27 | .name = "early", |
| 27 | .write = early_console_write, | 28 | .write = early_console_write, |
| 28 | .flags = CON_PRINTBUFFER | CON_BOOT, | 29 | .flags = CON_PRINTBUFFER | CON_BOOT, |
| 29 | .index = -1 | 30 | .index = -1 |
| 30 | }; | 31 | }; |
| 31 | 32 | ||
| 33 | static int early_console_initialized __initdata; | ||
| 34 | |||
| 32 | void __init setup_early_printk(void) | 35 | void __init setup_early_printk(void) |
| 33 | { | 36 | { |
| 37 | if (early_console_initialized) | ||
| 38 | return; | ||
| 39 | early_console_initialized = 1; | ||
| 40 | |||
| 34 | register_console(&early_console); | 41 | register_console(&early_console); |
| 35 | } | 42 | } |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 2967537221e2..410868b5ea5f 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
| @@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = { | |||
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | 134 | ||
| 135 | void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | 135 | void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) |
| 136 | { | 136 | { |
| 137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); | 137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); |
| 138 | 138 | ||
| 139 | _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000); | 139 | _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); |
| 140 | 140 | ||
| 141 | /* Reset interrupt controller - initialises all registers to 0 */ | 141 | /* Reset interrupt controller - initialises all registers to 0 */ |
| 142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); | 142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); |
| @@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
| 148 | 148 | ||
| 149 | switch (imp->im_type) { | 149 | switch (imp->im_type) { |
| 150 | case MSC01_IRQ_EDGE: | 150 | case MSC01_IRQ_EDGE: |
| 151 | set_irq_chip(base+n, &msc_edgeirq_type); | 151 | set_irq_chip(irqbase+n, &msc_edgeirq_type); |
| 152 | if (cpu_has_veic) | 152 | if (cpu_has_veic) |
| 153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
| 154 | else | 154 | else |
| 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
| 156 | break; | 156 | break; |
| 157 | case MSC01_IRQ_LEVEL: | 157 | case MSC01_IRQ_LEVEL: |
| 158 | set_irq_chip(base+n, &msc_levelirq_type); | 158 | set_irq_chip(irqbase+n, &msc_levelirq_type); |
| 159 | if (cpu_has_veic) | 159 | if (cpu_has_veic) |
| 160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
| 161 | else | 161 | else |
| @@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
| 163 | } | 163 | } |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | irq_base = base; | 166 | irq_base = irqbase; |
| 167 | 167 | ||
| 168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ | 168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ |
| 169 | 169 | ||
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 2fe4c868a801..aeded6c17de5 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; | 29 | static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; |
| 30 | 30 | ||
| 31 | int __devinit allocate_irqno(void) | 31 | int allocate_irqno(void) |
| 32 | { | 32 | { |
| 33 | int irq; | 33 | int irq; |
| 34 | 34 | ||
| @@ -59,7 +59,7 @@ void __init alloc_legacy_irqno(void) | |||
| 59 | BUG_ON(test_and_set_bit(i, irq_map)); | 59 | BUG_ON(test_and_set_bit(i, irq_map)); |
| 60 | } | 60 | } |
| 61 | 61 | ||
| 62 | void __devinit free_irqno(unsigned int irq) | 62 | void free_irqno(unsigned int irq) |
| 63 | { | 63 | { |
| 64 | smp_mb__before_clear_bit(); | 64 | smp_mb__before_clear_bit(); |
| 65 | clear_bit(irq, irq_map); | 65 | clear_bit(irq, irq_map); |
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index e5e56bd498db..751b4a18b133 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c | |||
| @@ -306,7 +306,7 @@ static unsigned int __init calibrate_hpt(void) | |||
| 306 | 306 | ||
| 307 | struct clocksource clocksource_mips = { | 307 | struct clocksource clocksource_mips = { |
| 308 | .name = "MIPS", | 308 | .name = "MIPS", |
| 309 | .mask = 0xffffffff, | 309 | .mask = CLOCKSOURCE_MASK(32), |
| 310 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 310 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 311 | }; | 311 | }; |
| 312 | 312 | ||
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ff45a4b8fbaa..200de027f354 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
| @@ -927,9 +927,9 @@ asmlinkage void do_reserved(struct pt_regs *regs) | |||
| 927 | (regs->cp0_cause & 0x7f) >> 2); | 927 | (regs->cp0_cause & 0x7f) >> 2); |
| 928 | } | 928 | } |
| 929 | 929 | ||
| 930 | asmlinkage void do_default_vi(struct pt_regs *regs) | 930 | static asmlinkage void do_default_vi(void) |
| 931 | { | 931 | { |
| 932 | show_regs(regs); | 932 | show_regs(get_irq_regs()); |
| 933 | panic("Caught unexpected vectored interrupt."); | 933 | panic("Caught unexpected vectored interrupt."); |
| 934 | } | 934 | } |
| 935 | 935 | ||
| @@ -1128,7 +1128,7 @@ void mips_srs_free(int set) | |||
| 1128 | clear_bit(set, &sr->sr_allocated); | 1128 | clear_bit(set, &sr->sr_allocated); |
| 1129 | } | 1129 | } |
| 1130 | 1130 | ||
| 1131 | static void *set_vi_srs_handler(int n, void *addr, int srs) | 1131 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
| 1132 | { | 1132 | { |
| 1133 | unsigned long handler; | 1133 | unsigned long handler; |
| 1134 | unsigned long old_handler = vi_handlers[n]; | 1134 | unsigned long old_handler = vi_handlers[n]; |
| @@ -1217,7 +1217,7 @@ static void *set_vi_srs_handler(int n, void *addr, int srs) | |||
| 1217 | return (void *)old_handler; | 1217 | return (void *)old_handler; |
| 1218 | } | 1218 | } |
| 1219 | 1219 | ||
| 1220 | void *set_vi_handler(int n, void *addr) | 1220 | void *set_vi_handler(int n, vi_handler_t addr) |
| 1221 | { | 1221 | { |
| 1222 | return set_vi_srs_handler(n, addr, 0); | 1222 | return set_vi_srs_handler(n, addr, 0); |
| 1223 | } | 1223 | } |
