diff options
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/i8259.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/irq-mv6434x.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/irq-rm7000.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/irq-rm9000.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/irq.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/irq_cpu.c | 4 |
7 files changed, 12 insertions, 12 deletions
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 0cb8ed5662f3..91ffb1233cad 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
@@ -120,7 +120,7 @@ int i8259A_irq_pending(unsigned int irq) | |||
120 | void make_8259A_irq(unsigned int irq) | 120 | void make_8259A_irq(unsigned int irq) |
121 | { | 121 | { |
122 | disable_irq_nosync(irq); | 122 | disable_irq_nosync(irq); |
123 | irq_desc[irq].handler = &i8259A_irq_type; | 123 | irq_desc[irq].chip = &i8259A_irq_type; |
124 | enable_irq(irq); | 124 | enable_irq(irq); |
125 | } | 125 | } |
126 | 126 | ||
@@ -327,7 +327,7 @@ void __init init_i8259_irqs (void) | |||
327 | irq_desc[i].status = IRQ_DISABLED; | 327 | irq_desc[i].status = IRQ_DISABLED; |
328 | irq_desc[i].action = NULL; | 328 | irq_desc[i].action = NULL; |
329 | irq_desc[i].depth = 1; | 329 | irq_desc[i].depth = 1; |
330 | irq_desc[i].handler = &i8259A_irq_type; | 330 | irq_desc[i].chip = &i8259A_irq_type; |
331 | } | 331 | } |
332 | 332 | ||
333 | setup_irq(2, &irq2); | 333 | setup_irq(2, &irq2); |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 97ebdc754b9e..f8cd1ac64d88 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -174,14 +174,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
174 | 174 | ||
175 | switch (imp->im_type) { | 175 | switch (imp->im_type) { |
176 | case MSC01_IRQ_EDGE: | 176 | case MSC01_IRQ_EDGE: |
177 | irq_desc[base+n].handler = &msc_edgeirq_type; | 177 | irq_desc[base+n].chip = &msc_edgeirq_type; |
178 | if (cpu_has_veic) | 178 | if (cpu_has_veic) |
179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
180 | else | 180 | else |
181 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 181 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
182 | break; | 182 | break; |
183 | case MSC01_IRQ_LEVEL: | 183 | case MSC01_IRQ_LEVEL: |
184 | irq_desc[base+n].handler = &msc_levelirq_type; | 184 | irq_desc[base+n].chip = &msc_levelirq_type; |
185 | if (cpu_has_veic) | 185 | if (cpu_has_veic) |
186 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 186 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
187 | else | 187 | else |
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 0613f1f36b1b..f9c763a65547 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c | |||
@@ -155,7 +155,7 @@ void __init mv64340_irq_init(unsigned int base) | |||
155 | irq_desc[i].status = IRQ_DISABLED; | 155 | irq_desc[i].status = IRQ_DISABLED; |
156 | irq_desc[i].action = 0; | 156 | irq_desc[i].action = 0; |
157 | irq_desc[i].depth = 2; | 157 | irq_desc[i].depth = 2; |
158 | irq_desc[i].handler = &mv64340_irq_type; | 158 | irq_desc[i].chip = &mv64340_irq_type; |
159 | } | 159 | } |
160 | 160 | ||
161 | irq_base = base; | 161 | irq_base = base; |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 0b130c5ac5d9..121da385a94d 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -91,7 +91,7 @@ void __init rm7k_cpu_irq_init(int base) | |||
91 | irq_desc[i].status = IRQ_DISABLED; | 91 | irq_desc[i].status = IRQ_DISABLED; |
92 | irq_desc[i].action = NULL; | 92 | irq_desc[i].action = NULL; |
93 | irq_desc[i].depth = 1; | 93 | irq_desc[i].depth = 1; |
94 | irq_desc[i].handler = &rm7k_irq_controller; | 94 | irq_desc[i].chip = &rm7k_irq_controller; |
95 | } | 95 | } |
96 | 96 | ||
97 | irq_base = base; | 97 | irq_base = base; |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 9b5f20c32acb..25109c103e44 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -139,11 +139,11 @@ void __init rm9k_cpu_irq_init(int base) | |||
139 | irq_desc[i].status = IRQ_DISABLED; | 139 | irq_desc[i].status = IRQ_DISABLED; |
140 | irq_desc[i].action = NULL; | 140 | irq_desc[i].action = NULL; |
141 | irq_desc[i].depth = 1; | 141 | irq_desc[i].depth = 1; |
142 | irq_desc[i].handler = &rm9k_irq_controller; | 142 | irq_desc[i].chip = &rm9k_irq_controller; |
143 | } | 143 | } |
144 | 144 | ||
145 | rm9000_perfcount_irq = base + 1; | 145 | rm9000_perfcount_irq = base + 1; |
146 | irq_desc[rm9000_perfcount_irq].handler = &rm9k_perfcounter_irq; | 146 | irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; |
147 | 147 | ||
148 | irq_base = base; | 148 | irq_base = base; |
149 | } | 149 | } |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 3dce742e716f..5c9dcd5eed59 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
@@ -95,7 +95,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
95 | for_each_online_cpu(j) | 95 | for_each_online_cpu(j) |
96 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 96 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
97 | #endif | 97 | #endif |
98 | seq_printf(p, " %14s", irq_desc[i].handler->typename); | 98 | seq_printf(p, " %14s", irq_desc[i].chip->typename); |
99 | seq_printf(p, " %s", action->name); | 99 | seq_printf(p, " %s", action->name); |
100 | 100 | ||
101 | for (action=action->next; action; action = action->next) | 101 | for (action=action->next; action; action = action->next) |
@@ -137,7 +137,7 @@ void __init init_IRQ(void) | |||
137 | irq_desc[i].status = IRQ_DISABLED; | 137 | irq_desc[i].status = IRQ_DISABLED; |
138 | irq_desc[i].action = NULL; | 138 | irq_desc[i].action = NULL; |
139 | irq_desc[i].depth = 1; | 139 | irq_desc[i].depth = 1; |
140 | irq_desc[i].handler = &no_irq_type; | 140 | irq_desc[i].chip = &no_irq_type; |
141 | spin_lock_init(&irq_desc[i].lock); | 141 | spin_lock_init(&irq_desc[i].lock); |
142 | #ifdef CONFIG_MIPS_MT_SMTC | 142 | #ifdef CONFIG_MIPS_MT_SMTC |
143 | irq_hwmask[i] = 0; | 143 | irq_hwmask[i] = 0; |
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 5db67e31ec1a..0e455a8ad860 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -167,14 +167,14 @@ void __init mips_cpu_irq_init(int irq_base) | |||
167 | irq_desc[i].status = IRQ_DISABLED; | 167 | irq_desc[i].status = IRQ_DISABLED; |
168 | irq_desc[i].action = NULL; | 168 | irq_desc[i].action = NULL; |
169 | irq_desc[i].depth = 1; | 169 | irq_desc[i].depth = 1; |
170 | irq_desc[i].handler = &mips_mt_cpu_irq_controller; | 170 | irq_desc[i].chip = &mips_mt_cpu_irq_controller; |
171 | } | 171 | } |
172 | 172 | ||
173 | for (i = irq_base + 2; i < irq_base + 8; i++) { | 173 | for (i = irq_base + 2; i < irq_base + 8; i++) { |
174 | irq_desc[i].status = IRQ_DISABLED; | 174 | irq_desc[i].status = IRQ_DISABLED; |
175 | irq_desc[i].action = NULL; | 175 | irq_desc[i].action = NULL; |
176 | irq_desc[i].depth = 1; | 176 | irq_desc[i].depth = 1; |
177 | irq_desc[i].handler = &mips_cpu_irq_controller; | 177 | irq_desc[i].chip = &mips_cpu_irq_controller; |
178 | } | 178 | } |
179 | 179 | ||
180 | mips_cpu_irq_base = irq_base; | 180 | mips_cpu_irq_base = irq_base; |