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-rw-r--r--arch/mips/kernel/apm.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/entry.S6
-rw-r--r--arch/mips/kernel/gdb-low.S4
-rw-r--r--arch/mips/kernel/genex.S2
-rw-r--r--arch/mips/kernel/head.S2
-rw-r--r--arch/mips/kernel/i8259.c4
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/irq-mv6434x.c2
-rw-r--r--arch/mips/kernel/irq-rm7000.c2
-rw-r--r--arch/mips/kernel/irq-rm9000.c4
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/irq_cpu.c4
-rw-r--r--arch/mips/kernel/r4k_switch.S6
-rw-r--r--arch/mips/kernel/scall32-o32.S1
-rw-r--r--arch/mips/kernel/scall64-64.S1
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/scall64-o32.S1
-rw-r--r--arch/mips/kernel/setup.c3
-rw-r--r--arch/mips/kernel/smp.c2
-rw-r--r--arch/mips/kernel/smtc-asm.S10
-rw-r--r--arch/mips/kernel/smtc.c4
-rw-r--r--arch/mips/kernel/syscall.c8
-rw-r--r--arch/mips/kernel/traps.c15
24 files changed, 51 insertions, 43 deletions
diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c
index 15f46b4471fd..7bdbcd811b57 100644
--- a/arch/mips/kernel/apm.c
+++ b/arch/mips/kernel/apm.c
@@ -260,7 +260,7 @@ static unsigned int apm_poll(struct file *fp, poll_table * wait)
260 * has acknowledge does the actual suspend happen. 260 * has acknowledge does the actual suspend happen.
261 */ 261 */
262static int 262static int
263apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) 263apm_ioctl(struct inode * inode, struct file *filp, unsigned int cmd, unsigned long arg)
264{ 264{
265 struct apm_user *as = filp->private_data; 265 struct apm_user *as = filp->private_data;
266 unsigned long flags; 266 unsigned long flags;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8c2c359a05f4..e045aba4ebda 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
597 break; 597 break;
598 case PRID_IMP_25KF: 598 case PRID_IMP_25KF:
599 c->cputype = CPU_25KF; 599 c->cputype = CPU_25KF;
600 /* Probe for L2 cache */
601 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
602 break; 600 break;
603 case PRID_IMP_34K: 601 case PRID_IMP_34K:
604 c->cputype = CPU_34K; 602 c->cputype = CPU_34K;
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index a9c6de1b9542..457565162dd5 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame
87 ori v1, v0, TCSTATUS_IXMT 87 ori v1, v0, TCSTATUS_IXMT
88 mtc0 v1, CP0_TCSTATUS 88 mtc0 v1, CP0_TCSTATUS
89 andi v0, TCSTATUS_IXMT 89 andi v0, TCSTATUS_IXMT
90 ehb 90 _ehb
91 mfc0 t0, CP0_TCCONTEXT 91 mfc0 t0, CP0_TCCONTEXT
92 DMT 9 # dmt t1 92 DMT 9 # dmt t1
93 jal mips_ihb 93 jal mips_ihb
@@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame
95 andi t3, t0, 0xff00 95 andi t3, t0, 0xff00
96 or t2, t2, t3 96 or t2, t2, t3
97 mtc0 t2, CP0_STATUS 97 mtc0 t2, CP0_STATUS
98 ehb 98 _ehb
99 andi t1, t1, VPECONTROL_TE 99 andi t1, t1, VPECONTROL_TE
100 beqz t1, 1f 100 beqz t1, 1f
101 EMT 101 EMT
@@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame
105 xori v1, v1, TCSTATUS_IXMT 105 xori v1, v1, TCSTATUS_IXMT
106 or v1, v0, v1 106 or v1, v0, v1
107 mtc0 v1, CP0_TCSTATUS 107 mtc0 v1, CP0_TCSTATUS
108 ehb 108 _ehb
109 xor t0, t0, t3 109 xor t0, t0, t3
110 mtc0 t0, CP0_TCCONTEXT 110 mtc0 t0, CP0_TCCONTEXT
111#endif /* CONFIG_MIPS_MT_SMTC */ 111#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
index 5fd7a8af0c62..8760131f89d9 100644
--- a/arch/mips/kernel/gdb-low.S
+++ b/arch/mips/kernel/gdb-low.S
@@ -291,7 +291,7 @@
291 ori t1, t2, TCSTATUS_IXMT 291 ori t1, t2, TCSTATUS_IXMT
292 mtc0 t1, CP0_TCSTATUS 292 mtc0 t1, CP0_TCSTATUS
293 andi t2, t2, TCSTATUS_IXMT 293 andi t2, t2, TCSTATUS_IXMT
294 ehb 294 _ehb
295 DMT 9 # dmt t1 295 DMT 9 # dmt t1
296 jal mips_ihb 296 jal mips_ihb
297 nop 297 nop
@@ -310,7 +310,7 @@
310 xori t1, t1, TCSTATUS_IXMT 310 xori t1, t1, TCSTATUS_IXMT
311 or t1, t1, t2 311 or t1, t1, t2
312 mtc0 t1, CP0_TCSTATUS 312 mtc0 t1, CP0_TCSTATUS
313 ehb 313 _ehb
314#endif /* CONFIG_MIPS_MT_SMTC */ 314#endif /* CONFIG_MIPS_MT_SMTC */
315 LONG_L v0, GDB_FR_STATUS(sp) 315 LONG_L v0, GDB_FR_STATUS(sp)
316 LONG_L v1, GDB_FR_EPC(sp) 316 LONG_L v1, GDB_FR_EPC(sp)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ff7af369f286..6888cde560af 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp)
214 mtc0 t0, CP0_TCCONTEXT 214 mtc0 t0, CP0_TCCONTEXT
215 xor t1, t1, t0 215 xor t1, t1, t0
216 mtc0 t1, CP0_STATUS 216 mtc0 t1, CP0_STATUS
217 ehb 217 _ehb
218#endif /* CONFIG_MIPS_MT_SMTC */ 218#endif /* CONFIG_MIPS_MT_SMTC */
219 CLI 219 CLI
220 move a0, sp 220 move a0, sp
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index bdf6f6eff721..c018098c9a56 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -96,7 +96,7 @@
96 /* Clear TKSU, leave IXMT */ 96 /* Clear TKSU, leave IXMT */
97 xori t0, 0x00001800 97 xori t0, 0x00001800
98 mtc0 t0, CP0_TCSTATUS 98 mtc0 t0, CP0_TCSTATUS
99 ehb 99 _ehb
100 /* We need to leave the global IE bit set, but clear EXL...*/ 100 /* We need to leave the global IE bit set, but clear EXL...*/
101 mfc0 t0, CP0_STATUS 101 mfc0 t0, CP0_STATUS
102 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr 102 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 0cb8ed5662f3..91ffb1233cad 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -120,7 +120,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 120void make_8259A_irq(unsigned int irq)
121{ 121{
122 disable_irq_nosync(irq); 122 disable_irq_nosync(irq);
123 irq_desc[irq].handler = &i8259A_irq_type; 123 irq_desc[irq].chip = &i8259A_irq_type;
124 enable_irq(irq); 124 enable_irq(irq);
125} 125}
126 126
@@ -327,7 +327,7 @@ void __init init_i8259_irqs (void)
327 irq_desc[i].status = IRQ_DISABLED; 327 irq_desc[i].status = IRQ_DISABLED;
328 irq_desc[i].action = NULL; 328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1; 329 irq_desc[i].depth = 1;
330 irq_desc[i].handler = &i8259A_irq_type; 330 irq_desc[i].chip = &i8259A_irq_type;
331 } 331 }
332 332
333 setup_irq(2, &irq2); 333 setup_irq(2, &irq2);
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 97ebdc754b9e..f8cd1ac64d88 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -174,14 +174,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
174 174
175 switch (imp->im_type) { 175 switch (imp->im_type) {
176 case MSC01_IRQ_EDGE: 176 case MSC01_IRQ_EDGE:
177 irq_desc[base+n].handler = &msc_edgeirq_type; 177 irq_desc[base+n].chip = &msc_edgeirq_type;
178 if (cpu_has_veic) 178 if (cpu_has_veic)
179 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 179 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
180 else 180 else
181 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 181 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
182 break; 182 break;
183 case MSC01_IRQ_LEVEL: 183 case MSC01_IRQ_LEVEL:
184 irq_desc[base+n].handler = &msc_levelirq_type; 184 irq_desc[base+n].chip = &msc_levelirq_type;
185 if (cpu_has_veic) 185 if (cpu_has_veic)
186 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 186 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
187 else 187 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 0613f1f36b1b..f9c763a65547 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -155,7 +155,7 @@ void __init mv64340_irq_init(unsigned int base)
155 irq_desc[i].status = IRQ_DISABLED; 155 irq_desc[i].status = IRQ_DISABLED;
156 irq_desc[i].action = 0; 156 irq_desc[i].action = 0;
157 irq_desc[i].depth = 2; 157 irq_desc[i].depth = 2;
158 irq_desc[i].handler = &mv64340_irq_type; 158 irq_desc[i].chip = &mv64340_irq_type;
159 } 159 }
160 160
161 irq_base = base; 161 irq_base = base;
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 0b130c5ac5d9..121da385a94d 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -91,7 +91,7 @@ void __init rm7k_cpu_irq_init(int base)
91 irq_desc[i].status = IRQ_DISABLED; 91 irq_desc[i].status = IRQ_DISABLED;
92 irq_desc[i].action = NULL; 92 irq_desc[i].action = NULL;
93 irq_desc[i].depth = 1; 93 irq_desc[i].depth = 1;
94 irq_desc[i].handler = &rm7k_irq_controller; 94 irq_desc[i].chip = &rm7k_irq_controller;
95 } 95 }
96 96
97 irq_base = base; 97 irq_base = base;
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 9b5f20c32acb..25109c103e44 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -139,11 +139,11 @@ void __init rm9k_cpu_irq_init(int base)
139 irq_desc[i].status = IRQ_DISABLED; 139 irq_desc[i].status = IRQ_DISABLED;
140 irq_desc[i].action = NULL; 140 irq_desc[i].action = NULL;
141 irq_desc[i].depth = 1; 141 irq_desc[i].depth = 1;
142 irq_desc[i].handler = &rm9k_irq_controller; 142 irq_desc[i].chip = &rm9k_irq_controller;
143 } 143 }
144 144
145 rm9000_perfcount_irq = base + 1; 145 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].handler = &rm9k_perfcounter_irq; 146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq;
147 147
148 irq_base = base; 148 irq_base = base;
149} 149}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 3dce742e716f..5c9dcd5eed59 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -95,7 +95,7 @@ int show_interrupts(struct seq_file *p, void *v)
95 for_each_online_cpu(j) 95 for_each_online_cpu(j)
96 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 96 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
97#endif 97#endif
98 seq_printf(p, " %14s", irq_desc[i].handler->typename); 98 seq_printf(p, " %14s", irq_desc[i].chip->typename);
99 seq_printf(p, " %s", action->name); 99 seq_printf(p, " %s", action->name);
100 100
101 for (action=action->next; action; action = action->next) 101 for (action=action->next; action; action = action->next)
@@ -137,7 +137,7 @@ void __init init_IRQ(void)
137 irq_desc[i].status = IRQ_DISABLED; 137 irq_desc[i].status = IRQ_DISABLED;
138 irq_desc[i].action = NULL; 138 irq_desc[i].action = NULL;
139 irq_desc[i].depth = 1; 139 irq_desc[i].depth = 1;
140 irq_desc[i].handler = &no_irq_type; 140 irq_desc[i].chip = &no_irq_type;
141 spin_lock_init(&irq_desc[i].lock); 141 spin_lock_init(&irq_desc[i].lock);
142#ifdef CONFIG_MIPS_MT_SMTC 142#ifdef CONFIG_MIPS_MT_SMTC
143 irq_hwmask[i] = 0; 143 irq_hwmask[i] = 0;
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 5db67e31ec1a..0e455a8ad860 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -167,14 +167,14 @@ void __init mips_cpu_irq_init(int irq_base)
167 irq_desc[i].status = IRQ_DISABLED; 167 irq_desc[i].status = IRQ_DISABLED;
168 irq_desc[i].action = NULL; 168 irq_desc[i].action = NULL;
169 irq_desc[i].depth = 1; 169 irq_desc[i].depth = 1;
170 irq_desc[i].handler = &mips_mt_cpu_irq_controller; 170 irq_desc[i].chip = &mips_mt_cpu_irq_controller;
171 } 171 }
172 172
173 for (i = irq_base + 2; i < irq_base + 8; i++) { 173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED; 174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL; 175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1; 176 irq_desc[i].depth = 1;
177 irq_desc[i].handler = &mips_cpu_irq_controller; 177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 } 178 }
179 179
180 mips_cpu_irq_base = irq_base; 180 mips_cpu_irq_base = irq_base;
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index db94e556fc97..e1b85e6c486a 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -94,7 +94,7 @@
94 ori t1, t2, TCSTATUS_IXMT 94 ori t1, t2, TCSTATUS_IXMT
95 mtc0 t1, CP0_TCSTATUS 95 mtc0 t1, CP0_TCSTATUS
96 andi t2, t2, TCSTATUS_IXMT 96 andi t2, t2, TCSTATUS_IXMT
97 ehb 97 _ehb
98 DMT 8 # dmt t0 98 DMT 8 # dmt t0
99 move t1,ra 99 move t1,ra
100 jal mips_ihb 100 jal mips_ihb
@@ -109,7 +109,7 @@
109 or a2, t1 109 or a2, t1
110 mtc0 a2, CP0_STATUS 110 mtc0 a2, CP0_STATUS
111#ifdef CONFIG_MIPS_MT_SMTC 111#ifdef CONFIG_MIPS_MT_SMTC
112 ehb 112 _ehb
113 andi t0, t0, VPECONTROL_TE 113 andi t0, t0, VPECONTROL_TE
114 beqz t0, 1f 114 beqz t0, 1f
115 emt 115 emt
@@ -118,7 +118,7 @@
118 xori t1, t1, TCSTATUS_IXMT 118 xori t1, t1, TCSTATUS_IXMT
119 or t1, t1, t2 119 or t1, t1, t2
120 mtc0 t1, CP0_TCSTATUS 120 mtc0 t1, CP0_TCSTATUS
121 ehb 121 _ehb
122#endif /* CONFIG_MIPS_MT_SMTC */ 122#endif /* CONFIG_MIPS_MT_SMTC */
123 move v0, a0 123 move v0, a0
124 jr ra 124 jr ra
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 2d2fdf77e308..6344be46ca8c 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -647,6 +647,7 @@ einval: li v0, -EINVAL
647 sys sys_unshare 1 647 sys sys_unshare 1
648 sys sys_splice 4 648 sys sys_splice 4
649 sys sys_sync_file_range 7 /* 4305 */ 649 sys sys_sync_file_range 7 /* 4305 */
650 sys sys_tee 4
650 .endm 651 .endm
651 652
652 /* We pre-compute the number of _instruction_ bytes needed to 653 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 9ba750887377..12d96c7d0bb2 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -462,3 +462,4 @@ sys_call_table:
462 PTR sys_unshare 462 PTR sys_unshare
463 PTR sys_splice 463 PTR sys_splice
464 PTR sys_sync_file_range 464 PTR sys_sync_file_range
465 PTR sys_tee /* 5265 */
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 942aca26f9c4..685698554a8a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -388,3 +388,4 @@ EXPORT(sysn32_call_table)
388 PTR sys_unshare 388 PTR sys_unshare
389 PTR sys_splice 389 PTR sys_splice
390 PTR sys_sync_file_range 390 PTR sys_sync_file_range
391 PTR sys_tee
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 8efb23a84131..0e632934cb76 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -510,4 +510,5 @@ sys_call_table:
510 PTR sys_unshare 510 PTR sys_unshare
511 PTR sys_splice 511 PTR sys_splice
512 PTR sys32_sync_file_range /* 4305 */ 512 PTR sys32_sync_file_range /* 4305 */
513 PTR sys_tee
513 .size sys_call_table,.-sys_call_table 514 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index bfcec8d9bfe4..d3e087115023 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -488,6 +488,9 @@ static inline void resource_init(void)
488{ 488{
489 int i; 489 int i;
490 490
491 if (UNCAC_BASE != IO_BASE)
492 return;
493
491 code_resource.start = virt_to_phys(&_text); 494 code_resource.start = virt_to_phys(&_text);
492 code_resource.end = virt_to_phys(&_etext) - 1; 495 code_resource.end = virt_to_phys(&_etext) - 1;
493 data_resource.start = virt_to_phys(&_etext); 496 data_resource.start = virt_to_phys(&_etext);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 298f82fe8440..9096a5ea4229 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -446,7 +446,7 @@ static int __init topology_init(void)
446 int ret; 446 int ret;
447 447
448 for_each_present_cpu(cpu) { 448 for_each_present_cpu(cpu) {
449 ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL); 449 ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu);
450 if (ret) 450 if (ret)
451 printk(KERN_WARNING "topology_init: register_cpu %d " 451 printk(KERN_WARNING "topology_init: register_cpu %d "
452 "failed (%d)\n", cpu, ret); 452 "failed (%d)\n", cpu, ret);
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index c9d65196d917..72c6d98f8854 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector)
52 .set noat 52 .set noat
53 /* Disable thread scheduling to make Status update atomic */ 53 /* Disable thread scheduling to make Status update atomic */
54 DMT 27 # dmt k1 54 DMT 27 # dmt k1
55 ehb 55 _ehb
56 /* Set EXL */ 56 /* Set EXL */
57 mfc0 k0,CP0_STATUS 57 mfc0 k0,CP0_STATUS
58 ori k0,k0,ST0_EXL 58 ori k0,k0,ST0_EXL
59 mtc0 k0,CP0_STATUS 59 mtc0 k0,CP0_STATUS
60 ehb 60 _ehb
61 /* Thread scheduling now inhibited by EXL. Restore TE state. */ 61 /* Thread scheduling now inhibited by EXL. Restore TE state. */
62 andi k1,k1,VPECONTROL_TE 62 andi k1,k1,VPECONTROL_TE
63 beqz k1,1f 63 beqz k1,1f
@@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector)
82 li k1,ST0_CU0 82 li k1,ST0_CU0
83 or k1,k1,k0 83 or k1,k1,k0
84 mtc0 k1,CP0_STATUS 84 mtc0 k1,CP0_STATUS
85 ehb 85 _ehb
86 get_saved_sp 86 get_saved_sp
87 /* Interrupting TC will have pre-set values in slots in the new frame */ 87 /* Interrupting TC will have pre-set values in slots in the new frame */
882: subu k1,k1,PT_SIZE 882: subu k1,k1,PT_SIZE
@@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector)
90 lw k0,PT_TCSTATUS(k1) 90 lw k0,PT_TCSTATUS(k1)
91 /* Write it to TCStatus to restore CU/KSU/IXMT state */ 91 /* Write it to TCStatus to restore CU/KSU/IXMT state */
92 mtc0 k0,$2,1 92 mtc0 k0,$2,1
93 ehb 93 _ehb
94 lw k0,PT_EPC(k1) 94 lw k0,PT_EPC(k1)
95 mtc0 k0,CP0_EPC 95 mtc0 k0,CP0_EPC
96 /* Save all will redundantly recompute the SP, but use it for now */ 96 /* Save all will redundantly recompute the SP, but use it for now */
@@ -116,7 +116,7 @@ LEAF(self_ipi)
116 mfc0 t0,CP0_TCSTATUS 116 mfc0 t0,CP0_TCSTATUS
117 ori t1,t0,TCSTATUS_IXMT 117 ori t1,t0,TCSTATUS_IXMT
118 mtc0 t1,CP0_TCSTATUS 118 mtc0 t1,CP0_TCSTATUS
119 ehb 119 _ehb
120 /* We know we're in kernel mode, so prepare stack frame */ 120 /* We know we're in kernel mode, so prepare stack frame */
121 subu t1,sp,PT_SIZE 121 subu t1,sp,PT_SIZE
122 sw ra,PT_EPC(t1) 122 sw ra,PT_EPC(t1)
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 2e8e52c135e6..70cf09afdf56 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -367,7 +367,7 @@ void mipsmt_prepare_cpus(void)
367 dvpe(); 367 dvpe();
368 dmt(); 368 dmt();
369 369
370 freeIPIq.lock = SPIN_LOCK_UNLOCKED; 370 spin_lock_init(&freeIPIq.lock);
371 371
372 /* 372 /*
373 * We probably don't have as many VPEs as we do SMP "CPUs", 373 * We probably don't have as many VPEs as we do SMP "CPUs",
@@ -375,7 +375,7 @@ void mipsmt_prepare_cpus(void)
375 */ 375 */
376 for (i=0; i<NR_CPUS; i++) { 376 for (i=0; i<NR_CPUS; i++) {
377 IPIQ[i].head = IPIQ[i].tail = NULL; 377 IPIQ[i].head = IPIQ[i].tail = NULL;
378 IPIQ[i].lock = SPIN_LOCK_UNLOCKED; 378 spin_lock_init(&IPIQ[i].lock);
379 IPIQ[i].depth = 0; 379 IPIQ[i].depth = 0;
380 ipi_timer_latch[i] = 0; 380 ipi_timer_latch[i] = 0;
381 } 381 }
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 5e8a18a8e2bd..6da8c68e89db 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -301,7 +301,7 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
301 * 301 *
302 * This is really horribly ugly. 302 * This is really horribly ugly.
303 */ 303 */
304asmlinkage int sys_ipc (uint call, int first, int second, 304asmlinkage int sys_ipc (unsigned int call, int first, int second,
305 unsigned long third, void __user *ptr, long fifth) 305 unsigned long third, void __user *ptr, long fifth)
306{ 306{
307 int version, ret; 307 int version, ret;
@@ -359,18 +359,18 @@ asmlinkage int sys_ipc (uint call, int first, int second,
359 case SHMAT: 359 case SHMAT:
360 switch (version) { 360 switch (version) {
361 default: { 361 default: {
362 ulong raddr; 362 unsigned long raddr;
363 ret = do_shmat (first, (char __user *) ptr, second, 363 ret = do_shmat (first, (char __user *) ptr, second,
364 &raddr); 364 &raddr);
365 if (ret) 365 if (ret)
366 return ret; 366 return ret;
367 return put_user (raddr, (ulong __user *) third); 367 return put_user (raddr, (unsigned long __user *) third);
368 } 368 }
369 case 1: /* iBCS2 emulator entry point */ 369 case 1: /* iBCS2 emulator entry point */
370 if (!segment_eq(get_fs(), get_ds())) 370 if (!segment_eq(get_fs(), get_ds()))
371 return -EINVAL; 371 return -EINVAL;
372 return do_shmat (first, (char __user *) ptr, second, 372 return do_shmat (first, (char __user *) ptr, second,
373 (ulong *) third); 373 (unsigned long *) third);
374 } 374 }
375 case SHMDT: 375 case SHMDT:
376 return sys_shmdt ((char __user *)ptr); 376 return sys_shmdt ((char __user *)ptr);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ad16eceb24dd..67971938a2cb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr)
1050 return (void *)old_handler; 1050 return (void *)old_handler;
1051} 1051}
1052 1052
1053#ifdef CONFIG_CPU_MIPSR2 1053#ifdef CONFIG_CPU_MIPSR2_SRS
1054/* 1054/*
1055 * MIPSR2 shadow register set allocation 1055 * MIPSR2 shadow register set allocation
1056 * FIXME: SMP... 1056 * FIXME: SMP...
@@ -1069,11 +1069,9 @@ static struct shadow_registers {
1069 1069
1070static void mips_srs_init(void) 1070static void mips_srs_init(void)
1071{ 1071{
1072#ifdef CONFIG_CPU_MIPSR2_SRS
1073 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1072 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1074 printk(KERN_INFO "%d MIPSR2 register sets available\n", 1073 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1075 shadow_registers.sr_supported); 1074 shadow_registers.sr_supported);
1076#endif
1077 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1075 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1078} 1076}
1079 1077
@@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr)
1198{ 1196{
1199 return set_vi_srs_handler(n, addr, 0); 1197 return set_vi_srs_handler(n, addr, 0);
1200} 1198}
1201#endif 1199
1200#else
1201
1202static inline void mips_srs_init(void)
1203{
1204}
1205
1206#endif /* CONFIG_CPU_MIPSR2_SRS */
1202 1207
1203/* 1208/*
1204 * This is used by native signal handling 1209 * This is used by native signal handling
@@ -1388,9 +1393,7 @@ void __init trap_init(void)
1388 else 1393 else
1389 ebase = CAC_BASE; 1394 ebase = CAC_BASE;
1390 1395
1391#ifdef CONFIG_CPU_MIPSR2
1392 mips_srs_init(); 1396 mips_srs_init();
1393#endif
1394 1397
1395 per_cpu_trap_init(); 1398 per_cpu_trap_init();
1396 1399
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 12:53:38 -0400