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-rw-r--r--arch/mips/kernel/Makefile5
-rw-r--r--arch/mips/kernel/asm-offsets.c31
-rw-r--r--arch/mips/kernel/branch.c33
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c31
-rw-r--r--arch/mips/kernel/csrc-r4k.c2
-rw-r--r--arch/mips/kernel/genex.S4
-rw-r--r--arch/mips/kernel/irq.c1
-rw-r--r--arch/mips/kernel/octeon_switch.S506
-rw-r--r--arch/mips/kernel/ptrace32.c64
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/traps.c21
12 files changed, 632 insertions, 70 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index b1372c27f136..e96122159928 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
9 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
10 10
11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 12obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o 14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
@@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
20obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 20obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
23 23
@@ -43,6 +43,7 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
46obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
46 47
47obj-$(CONFIG_SMP) += smp.o 48obj-$(CONFIG_SMP) += smp.o
48obj-$(CONFIG_SMP_UP) += smp-up.o 49obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 72942226fcdd..c901c22d7ad0 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -64,6 +64,10 @@ void output_ptreg_defines(void)
64#ifdef CONFIG_MIPS_MT_SMTC 64#ifdef CONFIG_MIPS_MT_SMTC
65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); 65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
66#endif /* CONFIG_MIPS_MT_SMTC */ 66#endif /* CONFIG_MIPS_MT_SMTC */
67#ifdef CONFIG_CPU_CAVIUM_OCTEON
68 OFFSET(PT_MPL, pt_regs, mpl);
69 OFFSET(PT_MTP, pt_regs, mtp);
70#endif /* CONFIG_CPU_CAVIUM_OCTEON */
67 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 71 DEFINE(PT_SIZE, sizeof(struct pt_regs));
68 BLANK(); 72 BLANK();
69} 73}
@@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void)
295 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); 299 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));
296 BLANK(); 300 BLANK();
297} 301}
302
303#ifdef CONFIG_CPU_CAVIUM_OCTEON
304void output_octeon_cop2_state_defines(void)
305{
306 COMMENT("Octeon specific octeon_cop2_state offsets.");
307 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
308 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
309 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
310 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
311 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
312 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
313 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
314 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
315 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
316 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
317 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
318 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
319 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
320 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
321 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
322 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
323 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
324 OFFSET(THREAD_CP2, task_struct, thread.cp2);
325 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
326 BLANK();
327}
328#endif
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 6b5df8bfab85..0176ed015c89 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -205,6 +205,39 @@ int __compute_return_epc(struct pt_regs *regs)
205 break; 205 break;
206 } 206 }
207 break; 207 break;
208#ifdef CONFIG_CPU_CAVIUM_OCTEON
209 case lwc2_op: /* This is bbit0 on Octeon */
210 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
211 == 0)
212 epc = epc + 4 + (insn.i_format.simmediate << 2);
213 else
214 epc += 8;
215 regs->cp0_epc = epc;
216 break;
217 case ldc2_op: /* This is bbit032 on Octeon */
218 if ((regs->regs[insn.i_format.rs] &
219 (1ull<<(insn.i_format.rt+32))) == 0)
220 epc = epc + 4 + (insn.i_format.simmediate << 2);
221 else
222 epc += 8;
223 regs->cp0_epc = epc;
224 break;
225 case swc2_op: /* This is bbit1 on Octeon */
226 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
227 epc = epc + 4 + (insn.i_format.simmediate << 2);
228 else
229 epc += 8;
230 regs->cp0_epc = epc;
231 break;
232 case sdc2_op: /* This is bbit132 on Octeon */
233 if (regs->regs[insn.i_format.rs] &
234 (1ull<<(insn.i_format.rt+32)))
235 epc = epc + 4 + (insn.i_format.simmediate << 2);
236 else
237 epc += 8;
238 regs->cp0_epc = epc;
239 break;
240#endif
208 } 241 }
209 242
210 return 0; 243 return 0;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e1ec83b68031..0015e442572b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -160,7 +160,7 @@ int c0_compare_int_usable(void)
160 160
161#ifndef CONFIG_MIPS_MT_SMTC 161#ifndef CONFIG_MIPS_MT_SMTC
162 162
163int __cpuinit mips_clockevent_init(void) 163int __cpuinit r4k_clockevent_init(void)
164{ 164{
165 uint64_t mips_freq = mips_hpt_frequency; 165 uint64_t mips_freq = mips_hpt_frequency;
166 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c9207b5fd923..a7162a4484cf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -96,6 +96,9 @@ int allow_au1k_wait;
96 96
97static void au1k_wait(void) 97static void au1k_wait(void)
98{ 98{
99 if (!allow_au1k_wait)
100 return;
101
99 /* using the wait instruction makes CP0 counter unusable */ 102 /* using the wait instruction makes CP0 counter unusable */
100 __asm__(" .set mips3 \n" 103 __asm__(" .set mips3 \n"
101 " cache 0x14, 0(%0) \n" 104 " cache 0x14, 0(%0) \n"
@@ -154,6 +157,7 @@ void __init check_wait(void)
154 case CPU_25KF: 157 case CPU_25KF:
155 case CPU_PR4450: 158 case CPU_PR4450:
156 case CPU_BCM3302: 159 case CPU_BCM3302:
160 case CPU_CAVIUM_OCTEON:
157 cpu_wait = r4k_wait; 161 cpu_wait = r4k_wait;
158 break; 162 break;
159 163
@@ -185,8 +189,7 @@ void __init check_wait(void)
185 case CPU_AU1200: 189 case CPU_AU1200:
186 case CPU_AU1210: 190 case CPU_AU1210:
187 case CPU_AU1250: 191 case CPU_AU1250:
188 if (allow_au1k_wait) 192 cpu_wait = au1k_wait;
189 cpu_wait = au1k_wait;
190 break; 193 break;
191 case CPU_20KC: 194 case CPU_20KC:
192 /* 195 /*
@@ -875,6 +878,27 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
875 } 878 }
876} 879}
877 880
881static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
882{
883 decode_configs(c);
884 switch (c->processor_id & 0xff00) {
885 case PRID_IMP_CAVIUM_CN38XX:
886 case PRID_IMP_CAVIUM_CN31XX:
887 case PRID_IMP_CAVIUM_CN30XX:
888 case PRID_IMP_CAVIUM_CN58XX:
889 case PRID_IMP_CAVIUM_CN56XX:
890 case PRID_IMP_CAVIUM_CN50XX:
891 case PRID_IMP_CAVIUM_CN52XX:
892 c->cputype = CPU_CAVIUM_OCTEON;
893 __cpu_name[cpu] = "Cavium Octeon";
894 break;
895 default:
896 printk(KERN_INFO "Unknown Octeon chip!\n");
897 c->cputype = CPU_UNKNOWN;
898 break;
899 }
900}
901
878const char *__cpu_name[NR_CPUS]; 902const char *__cpu_name[NR_CPUS];
879 903
880__cpuinit void cpu_probe(void) 904__cpuinit void cpu_probe(void)
@@ -909,6 +933,9 @@ __cpuinit void cpu_probe(void)
909 case PRID_COMP_NXP: 933 case PRID_COMP_NXP:
910 cpu_probe_nxp(c, cpu); 934 cpu_probe_nxp(c, cpu);
911 break; 935 break;
936 case PRID_COMP_CAVIUM:
937 cpu_probe_cavium(c, cpu);
938 break;
912 } 939 }
913 940
914 BUG_ON(!__cpu_name[cpu]); 941 BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 74fb74583b4e..f1a2893931ed 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = {
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 22 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
23}; 23};
24 24
25int __init init_mips_clocksource(void) 25int __init init_r4k_clocksource(void)
26{ 26{
27 if (!cpu_has_counter || !mips_hpt_frequency) 27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO; 28 return -ENXIO;
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 757d48f0d80f..fb6f73148df2 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -385,10 +385,14 @@ NESTED(nmi_handler, PT_SIZE, sp)
385 .endm 385 .endm
386 386
387 .macro __build_clear_fpe 387 .macro __build_clear_fpe
388 .set push
389 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
390 .set mips1
388 cfc1 a1, fcr31 391 cfc1 a1, fcr31
389 li a2, ~(0x3f << 12) 392 li a2, ~(0x3f << 12)
390 and a2, a1 393 and a2, a1
391 ctc1 a2, fcr31 394 ctc1 a2, fcr31
395 .set pop
392 TRACE_IRQS_ON 396 TRACE_IRQS_ON
393 STI 397 STI
394 .endm 398 .endm
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 4b4007b3083a..a0ff2b66e22b 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -111,6 +111,7 @@ int show_interrupts(struct seq_file *p, void *v)
111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
112#endif 112#endif
113 seq_printf(p, " %14s", irq_desc[i].chip->name); 113 seq_printf(p, " %14s", irq_desc[i].chip->name);
114 seq_printf(p, "-%-8s", irq_desc[i].name);
114 seq_printf(p, " %s", action->name); 115 seq_printf(p, " %s", action->name);
115 116
116 for (action=action->next; action; action = action->next) 117 for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
new file mode 100644
index 000000000000..d52389672b06
--- /dev/null
+++ b/arch/mips/kernel/octeon_switch.S
@@ -0,0 +1,506 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/fpregdef.h>
16#include <asm/mipsregs.h>
17#include <asm/asm-offsets.h>
18#include <asm/page.h>
19#include <asm/pgtable-bits.h>
20#include <asm/regdef.h>
21#include <asm/stackframe.h>
22#include <asm/thread_info.h>
23
24#include <asm/asmmacro.h>
25
26/*
27 * Offset to the current process status flags, the first 32 bytes of the
28 * stack are not used.
29 */
30#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
31
32/*
33 * task_struct *resume(task_struct *prev, task_struct *next,
34 * struct thread_info *next_ti)
35 */
36 .align 7
37 LEAF(resume)
38 .set arch=octeon
39#ifndef CONFIG_CPU_HAS_LLSC
40 sw zero, ll_bit
41#endif
42 mfc0 t1, CP0_STATUS
43 LONG_S t1, THREAD_STATUS(a0)
44 cpu_save_nonscratch a0
45 LONG_S ra, THREAD_REG31(a0)
46
47 /* check if we need to save COP2 registers */
48 PTR_L t2, TASK_THREAD_INFO(a0)
49 LONG_L t0, ST_OFF(t2)
50 bbit0 t0, 30, 1f
51
52 /* Disable COP2 in the stored process state */
53 li t1, ST0_CU2
54 xor t0, t1
55 LONG_S t0, ST_OFF(t2)
56
57 /* Enable COP2 so we can save it */
58 mfc0 t0, CP0_STATUS
59 or t0, t1
60 mtc0 t0, CP0_STATUS
61
62 /* Save COP2 */
63 daddu a0, THREAD_CP2
64 jal octeon_cop2_save
65 dsubu a0, THREAD_CP2
66
67 /* Disable COP2 now that we are done */
68 mfc0 t0, CP0_STATUS
69 li t1, ST0_CU2
70 xor t0, t1
71 mtc0 t0, CP0_STATUS
72
731:
74#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
75 /* Check if we need to store CVMSEG state */
76 mfc0 t0, $11,7 /* CvmMemCtl */
77 bbit0 t0, 6, 3f /* Is user access enabled? */
78
79 /* Store the CVMSEG state */
80 /* Extract the size of CVMSEG */
81 andi t0, 0x3f
82 /* Multiply * (cache line size/sizeof(long)/2) */
83 sll t0, 7-LONGLOG-1
84 li t1, -32768 /* Base address of CVMSEG */
85 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
86 synciobdma
872:
88 .set noreorder
89 LONG_L t8, 0(t1) /* Load from CVMSEG */
90 subu t0, 1 /* Decrement loop var */
91 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
92 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
93 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
94 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
95 bnez t0, 2b /* Loop until we've copied it all */
96 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
97 .set reorder
98
99 /* Disable access to CVMSEG */
100 mfc0 t0, $11,7 /* CvmMemCtl */
101 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
102 mtc0 t0, $11,7 /* CvmMemCtl */
103#endif
1043:
105 /*
106 * The order of restoring the registers takes care of the race
107 * updating $28, $29 and kernelsp without disabling ints.
108 */
109 move $28, a2
110 cpu_restore_nonscratch a1
111
112#if (_THREAD_SIZE - 32) < 0x8000
113 PTR_ADDIU t0, $28, _THREAD_SIZE - 32
114#else
115 PTR_LI t0, _THREAD_SIZE - 32
116 PTR_ADDU t0, $28
117#endif
118 set_saved_sp t0, t1, t2
119
120 mfc0 t1, CP0_STATUS /* Do we really need this? */
121 li a3, 0xff01
122 and t1, a3
123 LONG_L a2, THREAD_STATUS(a1)
124 nor a3, $0, a3
125 and a2, a3
126 or a2, t1
127 mtc0 a2, CP0_STATUS
128 move v0, a0
129 jr ra
130 END(resume)
131
132/*
133 * void octeon_cop2_save(struct octeon_cop2_state *a0)
134 */
135 .align 7
136 LEAF(octeon_cop2_save)
137
138 dmfc0 t9, $9,7 /* CvmCtl register. */
139
140 /* Save the COP2 CRC state */
141 dmfc2 t0, 0x0201
142 dmfc2 t1, 0x0202
143 dmfc2 t2, 0x0200
144 sd t0, OCTEON_CP2_CRC_IV(a0)
145 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
146 sd t2, OCTEON_CP2_CRC_POLY(a0)
147 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
148 bbit1 t9, 28, 1f
149
150 /* Save the LLM state */
151 dmfc2 t0, 0x0402
152 dmfc2 t1, 0x040A
153 sd t0, OCTEON_CP2_LLM_DAT(a0)
154 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
155
1561: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
157
158 /* Save the COP2 crypto state */
159 /* this part is mostly common to both pass 1 and later revisions */
160 dmfc2 t0, 0x0084
161 dmfc2 t1, 0x0080
162 dmfc2 t2, 0x0081
163 dmfc2 t3, 0x0082
164 sd t0, OCTEON_CP2_3DES_IV(a0)
165 dmfc2 t0, 0x0088
166 sd t1, OCTEON_CP2_3DES_KEY(a0)
167 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
168 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
169 dmfc2 t2, 0x0102
170 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
171 dmfc2 t3, 0x0103
172 sd t0, OCTEON_CP2_3DES_RESULT(a0)
173 dmfc2 t0, 0x0104
174 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
175 dmfc2 t1, 0x0105
176 sd t2, OCTEON_CP2_AES_IV(a0)
177 dmfc2 t2, 0x0106
178 sd t3, OCTEON_CP2_AES_IV+8(a0)
179 dmfc2 t3, 0x0107
180 sd t0, OCTEON_CP2_AES_KEY(a0)
181 dmfc2 t0, 0x0110
182 sd t1, OCTEON_CP2_AES_KEY+8(a0)
183 dmfc2 t1, 0x0100
184 sd t2, OCTEON_CP2_AES_KEY+16(a0)
185 dmfc2 t2, 0x0101
186 sd t3, OCTEON_CP2_AES_KEY+24(a0)
187 mfc0 t3, $15,0 /* Get the processor ID register */
188 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
189 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
190 sd t1, OCTEON_CP2_AES_RESULT(a0)
191 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
192 /* Skip to the Pass1 version of the remainder of the COP2 state */
193 beq t3, t0, 2f
194
195 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
196 dmfc2 t1, 0x0240
197 dmfc2 t2, 0x0241
198 dmfc2 t3, 0x0242
199 dmfc2 t0, 0x0243
200 sd t1, OCTEON_CP2_HSH_DATW(a0)
201 dmfc2 t1, 0x0244
202 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
203 dmfc2 t2, 0x0245
204 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
205 dmfc2 t3, 0x0246
206 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
207 dmfc2 t0, 0x0247
208 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
209 dmfc2 t1, 0x0248
210 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
211 dmfc2 t2, 0x0249
212 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
213 dmfc2 t3, 0x024A
214 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
215 dmfc2 t0, 0x024B
216 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
217 dmfc2 t1, 0x024C
218 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
219 dmfc2 t2, 0x024D
220 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
221 dmfc2 t3, 0x024E
222 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
223 dmfc2 t0, 0x0250
224 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
225 dmfc2 t1, 0x0251
226 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
227 dmfc2 t2, 0x0252
228 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
229 dmfc2 t3, 0x0253
230 sd t0, OCTEON_CP2_HSH_IVW(a0)
231 dmfc2 t0, 0x0254
232 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
233 dmfc2 t1, 0x0255
234 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
235 dmfc2 t2, 0x0256
236 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
237 dmfc2 t3, 0x0257
238 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
239 dmfc2 t0, 0x0258
240 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
241 dmfc2 t1, 0x0259
242 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
243 dmfc2 t2, 0x025E
244 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
245 dmfc2 t3, 0x025A
246 sd t0, OCTEON_CP2_GFM_MULT(a0)
247 dmfc2 t0, 0x025B
248 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
249 sd t2, OCTEON_CP2_GFM_POLY(a0)
250 sd t3, OCTEON_CP2_GFM_RESULT(a0)
251 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
252 jr ra
253
2542: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
255 dmfc2 t3, 0x0040
256 dmfc2 t0, 0x0041
257 dmfc2 t1, 0x0042
258 dmfc2 t2, 0x0043
259 sd t3, OCTEON_CP2_HSH_DATW(a0)
260 dmfc2 t3, 0x0044
261 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
262 dmfc2 t0, 0x0045
263 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
264 dmfc2 t1, 0x0046
265 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
266 dmfc2 t2, 0x0048
267 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
268 dmfc2 t3, 0x0049
269 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
270 dmfc2 t0, 0x004A
271 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
272 sd t2, OCTEON_CP2_HSH_IVW(a0)
273 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
274 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
275
2763: /* pass 1 or CvmCtl[NOCRYPTO] set */
277 jr ra
278 END(octeon_cop2_save)
279
280/*
281 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
282 */
283 .align 7
284 .set push
285 .set noreorder
286 LEAF(octeon_cop2_restore)
287 /* First cache line was prefetched before the call */
288 pref 4, 128(a0)
289 dmfc0 t9, $9,7 /* CvmCtl register. */
290
291 pref 4, 256(a0)
292 ld t0, OCTEON_CP2_CRC_IV(a0)
293 pref 4, 384(a0)
294 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
295 ld t2, OCTEON_CP2_CRC_POLY(a0)
296
297 /* Restore the COP2 CRC state */
298 dmtc2 t0, 0x0201
299 dmtc2 t1, 0x1202
300 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
301 dmtc2 t2, 0x4200
302
303 /* Restore the LLM state */
304 ld t0, OCTEON_CP2_LLM_DAT(a0)
305 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
306 dmtc2 t0, 0x0402
307 dmtc2 t1, 0x040A
308
3092:
310 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
311 nop
312
313 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
314 ld t0, OCTEON_CP2_3DES_IV(a0)
315 ld t1, OCTEON_CP2_3DES_KEY(a0)
316 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
317 dmtc2 t0, 0x0084
318 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
319 dmtc2 t1, 0x0080
320 ld t1, OCTEON_CP2_3DES_RESULT(a0)
321 dmtc2 t2, 0x0081
322 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
323 dmtc2 t0, 0x0082
324 ld t0, OCTEON_CP2_AES_IV(a0)
325 dmtc2 t1, 0x0098
326 ld t1, OCTEON_CP2_AES_IV+8(a0)
327 dmtc2 t2, 0x010A /* only really needed for pass 1 */
328 ld t2, OCTEON_CP2_AES_KEY(a0)
329 dmtc2 t0, 0x0102
330 ld t0, OCTEON_CP2_AES_KEY+8(a0)
331 dmtc2 t1, 0x0103
332 ld t1, OCTEON_CP2_AES_KEY+16(a0)
333 dmtc2 t2, 0x0104
334 ld t2, OCTEON_CP2_AES_KEY+24(a0)
335 dmtc2 t0, 0x0105
336 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
337 dmtc2 t1, 0x0106
338 ld t1, OCTEON_CP2_AES_RESULT(a0)
339 dmtc2 t2, 0x0107
340 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
341 mfc0 t3, $15,0 /* Get the processor ID register */
342 dmtc2 t0, 0x0110
343 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
344 dmtc2 t1, 0x0100
345 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
346 dmtc2 t2, 0x0101
347
348 /* this code is specific for pass 1 */
349 ld t0, OCTEON_CP2_HSH_DATW(a0)
350 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
351 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
352 dmtc2 t0, 0x0040
353 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
354 dmtc2 t1, 0x0041
355 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
356 dmtc2 t2, 0x0042
357 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
358 dmtc2 t0, 0x0043
359 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
360 dmtc2 t1, 0x0044
361 ld t1, OCTEON_CP2_HSH_IVW(a0)
362 dmtc2 t2, 0x0045
363 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
364 dmtc2 t0, 0x0046
365 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
366 dmtc2 t1, 0x0048
367 dmtc2 t2, 0x0049
368 b done_restore /* unconditional branch */
369 dmtc2 t0, 0x004A
370
3713: /* this is post-pass1 code */
372 ld t2, OCTEON_CP2_HSH_DATW(a0)
373 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
374 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
375 dmtc2 t2, 0x0240
376 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
377 dmtc2 t0, 0x0241
378 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
379 dmtc2 t1, 0x0242
380 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
381 dmtc2 t2, 0x0243
382 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
383 dmtc2 t0, 0x0244
384 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
385 dmtc2 t1, 0x0245
386 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
387 dmtc2 t2, 0x0246
388 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
389 dmtc2 t0, 0x0247
390 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
391 dmtc2 t1, 0x0248
392 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
393 dmtc2 t2, 0x0249
394 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
395 dmtc2 t0, 0x024A
396 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
397 dmtc2 t1, 0x024B
398 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
399 dmtc2 t2, 0x024C
400 ld t2, OCTEON_CP2_HSH_IVW(a0)
401 dmtc2 t0, 0x024D
402 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
403 dmtc2 t1, 0x024E
404 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
405 dmtc2 t2, 0x0250
406 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
407 dmtc2 t0, 0x0251
408 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
409 dmtc2 t1, 0x0252
410 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
411 dmtc2 t2, 0x0253
412 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
413 dmtc2 t0, 0x0254
414 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
415 dmtc2 t1, 0x0255
416 ld t1, OCTEON_CP2_GFM_MULT(a0)
417 dmtc2 t2, 0x0256
418 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
419 dmtc2 t0, 0x0257
420 ld t0, OCTEON_CP2_GFM_POLY(a0)
421 dmtc2 t1, 0x0258
422 ld t1, OCTEON_CP2_GFM_RESULT(a0)
423 dmtc2 t2, 0x0259
424 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
425 dmtc2 t0, 0x025E
426 dmtc2 t1, 0x025A
427 dmtc2 t2, 0x025B
428
429done_restore:
430 jr ra
431 nop
432 END(octeon_cop2_restore)
433 .set pop
434
435/*
436 * void octeon_mult_save()
437 * sp is assumed to point to a struct pt_regs
438 *
439 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
440 * safely modify k0 and k1.
441 */
442 .align 7
443 .set push
444 .set noreorder
445 LEAF(octeon_mult_save)
446 dmfc0 k0, $9,7 /* CvmCtl register. */
447 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
448 nop
449
450 /* Save the multiplier state */
451 v3mulu k0, $0, $0
452 v3mulu k1, $0, $0
453 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
454 v3mulu k0, $0, $0
455 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
456 ori k1, $0, 1
457 v3mulu k1, k1, $0
458 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
459 v3mulu k0, $0, $0
460 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
461 v3mulu k1, $0, $0
462 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
463 jr ra
464 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
465
4661: /* Resume here if CvmCtl[NOMUL] */
467 jr ra
468 END(octeon_mult_save)
469 .set pop
470
471/*
472 * void octeon_mult_restore()
473 * sp is assumed to point to a struct pt_regs
474 *
475 * NOTE: This is called in RESTORE_SOME in stackframe.h.
476 */
477 .align 7
478 .set push
479 .set noreorder
480 LEAF(octeon_mult_restore)
481 dmfc0 k1, $9,7 /* CvmCtl register. */
482 ld v0, PT_MPL(sp) /* MPL0 */
483 ld v1, PT_MPL+8(sp) /* MPL1 */
484 ld k0, PT_MPL+16(sp) /* MPL2 */
485 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
486 /* Normally falls through, so no time wasted here */
487 nop
488
489 /* Restore the multiplier state */
490 ld k1, PT_MTP+16(sp) /* P2 */
491 MTM0 v0 /* MPL0 */
492 ld v0, PT_MTP+8(sp) /* P1 */
493 MTM1 v1 /* MPL1 */
494 ld v1, PT_MTP(sp) /* P0 */
495 MTM2 k0 /* MPL2 */
496 MTP2 k1 /* P2 */
497 MTP1 v0 /* P1 */
498 jr ra
499 MTP0 v1 /* P0 */
500
5011: /* Resume here if CvmCtl[NOMUL] */
502 jr ra
503 nop
504 END(octeon_mult_restore)
505 .set pop
506
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 1ca34104e593..c4f9ac17474a 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -49,19 +49,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
49 int ret; 49 int ret;
50 50
51 switch (request) { 51 switch (request) {
52 /* when I and D space are separate, these will need to be fixed. */
53 case PTRACE_PEEKTEXT: /* read word at location addr. */
54 case PTRACE_PEEKDATA: {
55 unsigned int tmp;
56 int copied;
57
58 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
59 ret = -EIO;
60 if (copied != sizeof(tmp))
61 break;
62 ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
63 break;
64 }
65 52
66 /* 53 /*
67 * Read 4 bytes of the other process' storage 54 * Read 4 bytes of the other process' storage
@@ -208,16 +195,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
208 break; 195 break;
209 } 196 }
210 197
211 /* when I and D space are separate, this will have to be fixed. */
212 case PTRACE_POKETEXT: /* write the word at location addr. */
213 case PTRACE_POKEDATA:
214 ret = 0;
215 if (access_process_vm(child, addr, &data, sizeof(data), 1)
216 == sizeof(data))
217 break;
218 ret = -EIO;
219 break;
220
221 /* 198 /*
222 * Write 4 bytes into the other process' storage 199 * Write 4 bytes into the other process' storage
223 * data is the 4 bytes that the user wants written 200 * data is the 4 bytes that the user wants written
@@ -332,50 +309,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
332 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); 309 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
333 break; 310 break;
334 311
335 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
336 case PTRACE_CONT: { /* restart after signal. */
337 ret = -EIO;
338 if (!valid_signal(data))
339 break;
340 if (request == PTRACE_SYSCALL) {
341 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
342 }
343 else {
344 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
345 }
346 child->exit_code = data;
347 wake_up_process(child);
348 ret = 0;
349 break;
350 }
351
352 /*
353 * make the child exit. Best I can do is send it a sigkill.
354 * perhaps it should be put in the status that it wants to
355 * exit.
356 */
357 case PTRACE_KILL:
358 ret = 0;
359 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
360 break;
361 child->exit_code = SIGKILL;
362 wake_up_process(child);
363 break;
364
365 case PTRACE_GET_THREAD_AREA: 312 case PTRACE_GET_THREAD_AREA:
366 ret = put_user(task_thread_info(child)->tp_value, 313 ret = put_user(task_thread_info(child)->tp_value,
367 (unsigned int __user *) (unsigned long) data); 314 (unsigned int __user *) (unsigned long) data);
368 break; 315 break;
369 316
370 case PTRACE_DETACH: /* detach a process that was attached. */
371 ret = ptrace_detach(child, data);
372 break;
373
374 case PTRACE_GETEVENTMSG:
375 ret = put_user(child->ptrace_message,
376 (unsigned int __user *) (unsigned long) data);
377 break;
378
379 case PTRACE_GET_THREAD_AREA_3264: 317 case PTRACE_GET_THREAD_AREA_3264:
380 ret = put_user(task_thread_info(child)->tp_value, 318 ret = put_user(task_thread_info(child)->tp_value,
381 (unsigned long __user *) (unsigned long) data); 319 (unsigned long __user *) (unsigned long) data);
@@ -392,7 +330,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
392 break; 330 break;
393 331
394 default: 332 default:
395 ret = ptrace_request(child, request, addr, data); 333 ret = compat_ptrace_request(child, request, addr, data);
396 break; 334 break;
397 } 335 }
398out: 336out:
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index d0916a55cd77..51d1ba415b90 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -398,7 +398,7 @@ einval: li v0, -ENOSYS
398 sys sys_uselib 1 398 sys sys_uselib 1
399 sys sys_swapon 2 399 sys sys_swapon 2
400 sys sys_reboot 3 400 sys sys_reboot 3
401 sys old_readdir 3 401 sys sys_old_readdir 3
402 sys old_mmap 6 /* 4090 */ 402 sys old_mmap 6 /* 4090 */
403 sys sys_munmap 2 403 sys sys_munmap 2
404 sys sys_truncate 2 404 sys sys_truncate 2
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 353056110f2b..f6083c6bfaa4 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -47,6 +47,7 @@
47#include <asm/mmu_context.h> 47#include <asm/mmu_context.h>
48#include <asm/types.h> 48#include <asm/types.h>
49#include <asm/stacktrace.h> 49#include <asm/stacktrace.h>
50#include <asm/irq.h>
50 51
51extern void check_wait(void); 52extern void check_wait(void);
52extern asmlinkage void r4k_wait(void); 53extern asmlinkage void r4k_wait(void);
@@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void);
78extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
79 struct mips_fpu_struct *ctx, int has_fpu); 80 struct mips_fpu_struct *ctx, int has_fpu);
80 81
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
81void (*board_be_init)(void); 86void (*board_be_init)(void);
82int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 87int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
83void (*board_nmi_handler_setup)(void); 88void (*board_nmi_handler_setup)(void);
@@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
860 unsigned int opcode; 865 unsigned int opcode;
861 unsigned int cpid; 866 unsigned int cpid;
862 int status; 867 int status;
868 unsigned long __maybe_unused flags;
863 869
864 die_if_kernel("do_cpu invoked from kernel context!", regs); 870 die_if_kernel("do_cpu invoked from kernel context!", regs);
865 871
@@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs)
915 return; 921 return;
916 922
917 case 2: 923 case 2:
924#ifdef CONFIG_CPU_CAVIUM_OCTEON
925 prefetch(&current->thread.cp2);
926 local_irq_save(flags);
927 KSTK_STATUS(current) |= ST0_CU2;
928 status = read_c0_status();
929 write_c0_status(status | ST0_CU2);
930 octeon_cop2_restore(&(current->thread.cp2));
931 write_c0_status(status & ~ST0_CU2);
932 local_irq_restore(flags);
933 return;
934#endif
918 case 3: 935 case 3:
919 break; 936 break;
920 } 937 }
@@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void)
1488 write_c0_hwrena(enable); 1505 write_c0_hwrena(enable);
1489 } 1506 }
1490 1507
1508#ifdef CONFIG_CPU_CAVIUM_OCTEON
1509 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
1510#endif
1511
1491#ifdef CONFIG_MIPS_MT_SMTC 1512#ifdef CONFIG_MIPS_MT_SMTC
1492 if (!secondaryTC) { 1513 if (!secondaryTC) {
1493#endif /* CONFIG_MIPS_MT_SMTC */ 1514#endif /* CONFIG_MIPS_MT_SMTC */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 17:23:34 -0500