diff options
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/irq_cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 2b936cf1ef70..8f8c15fa748d 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -3,6 +3,8 @@ | |||
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
4 | * | 4 | * |
5 | * Copyright (C) 2001 Ralf Baechle | 5 | * Copyright (C) 2001 Ralf Baechle |
6 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. | ||
7 | * Author: Maciej W. Rozycki <macro@mips.com> | ||
6 | * | 8 | * |
7 | * This file define the irq handler for MIPS CPU interrupts. | 9 | * This file define the irq handler for MIPS CPU interrupts. |
8 | * | 10 | * |
@@ -37,7 +39,6 @@ static int mips_cpu_irq_base; | |||
37 | 39 | ||
38 | static inline void unmask_mips_irq(unsigned int irq) | 40 | static inline void unmask_mips_irq(unsigned int irq) |
39 | { | 41 | { |
40 | clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); | ||
41 | set_c0_status(0x100 << (irq - mips_cpu_irq_base)); | 42 | set_c0_status(0x100 << (irq - mips_cpu_irq_base)); |
42 | } | 43 | } |
43 | 44 | ||
@@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base) | |||
107 | { | 108 | { |
108 | int i; | 109 | int i; |
109 | 110 | ||
111 | /* Mask interrupts. */ | ||
112 | clear_c0_status(ST0_IM); | ||
113 | clear_c0_cause(CAUSEF_IP); | ||
114 | |||
110 | for (i = irq_base; i < irq_base + 8; i++) { | 115 | for (i = irq_base; i < irq_base + 8; i++) { |
111 | irq_desc[i].status = IRQ_DISABLED; | 116 | irq_desc[i].status = IRQ_DISABLED; |
112 | irq_desc[i].action = NULL; | 117 | irq_desc[i].action = NULL; |