3 files changed, 19 insertions, 4 deletions

diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 87e88feb4a25..6cbbf6e106b9 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -37,7 +37,7 @@ static struct clocksource clocksource_dec = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-void __init dec_ioasic_clocksource_init(void)
+int __init dec_ioasic_clocksource_init(void)
 {
         unsigned int freq;
         u32 start, end;
@@ -56,8 +56,14 @@ void __init dec_ioasic_clocksource_init(void)
         end = dec_ioasic_hpt_read(&clocksource_dec);
 
         freq = (end - start) * 8;
+
+        /* An early revision of the I/O ASIC didn't have the counter.  */
+        if (!freq)
+                return -ENXIO;
+
         printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
 
         clocksource_dec.rating = 200 + freq / 10000000;
         clocksource_register_hz(&clocksource_dec, freq);
+        return 0;
 }
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index c2e5d74739b4..5969f1e9b62a 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
 
         c->core = (read_c0_ebase() >> 1) & 0x1ff;
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
-        c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
+        if (cpu_has_mipsmt)
+                c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
+                        TCBIND_CURVPE;
 #endif
 #ifdef CONFIG_MIPS_MT_SMTC
         c->tc_id  = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
@@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
         }
 
         if (cpu_has_mipsmt) {
-                unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
+                unsigned int nvpe = 1;
+#ifdef CONFIG_MIPS_MT_SMP
+                unsigned int mvpconf0 = read_c0_mvpconf0();
+
+                nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+#elif defined(CONFIG_MIPS_MT_SMTC)
+                unsigned int mvpconf0 = read_c0_mvpconf0();
 
                 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
+#endif
                 smp_num_siblings = nvpe;
         }
         pr_info("Detected %i available secondary CPU(s)\n", ncpu);
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index faf84c5f2629..59b2b3cd7885 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1368,7 +1368,7 @@ out_einval:
 }
 static DEVICE_ATTR_RW(ntcs);
 
-static struct attribute vpe_attrs[] = {
+static struct attribute *vpe_attrs[] = {
         &dev_attr_kill.attr,
         &dev_attr_ntcs.attr,
         NULL,