3 files changed, 230 insertions, 0 deletions

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 6fcdb6fda2e2..67d97fb02c38 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MIPS_MT)		+= mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)     += mips-mt-fpaff.o
 obj-$(CONFIG_MIPS_MT_SMTC)      += smtc.o smtc-asm.o smtc-proc.o
 obj-$(CONFIG_MIPS_MT_SMP)       += smp-mt.o
+obj-$(CONFIG_CPU_MIPSR2)        += spram.o
 
 obj-$(CONFIG_MIPS_APSP_KSPD)    += kspd.o
 obj-$(CONFIG_MIPS_VPE_LOADER)   += vpe.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 89c3304cb93c..add717dccf77 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -675,6 +675,12 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                 return;
 }
 
+#ifdef CONFIG_CPU_MIPSR2
+extern void spram_config(void);
+#else
+static inline void spram_config(void) {}
+#endif
+
 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 {
         decode_configs(c);
@@ -712,6 +718,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                 c->cputype = CPU_74K;
                 break;
         }
+
+        spram_config();
 }
 
 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
new file mode 100644
index 000000000000..6ddb507a87ef
--- /dev/null
+++ b/arch/mips/kernel/spram.c
@@ -0,0 +1,221 @@
+/*
+ * MIPS SPRAM support
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/stddef.h>
+
+#include <asm/cpu.h>
+#include <asm/fpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/r4kcache.h>
+#include <asm/hazards.h>
+
+/*
+ * These definitions are correct for the 24K/34K/74K SPRAM sample
+ * implementation. The 4KS interpreted the tags differently...
+ */
+#define SPRAM_TAG0_ENABLE       0x00000080
+#define SPRAM_TAG0_PA_MASK      0xfffff000
+#define SPRAM_TAG1_SIZE_MASK    0xfffff000
+
+#define SPRAM_TAG_STRIDE        8
+
+#define ERRCTL_SPRAM            (1 << 28)
+
+/* errctl access */
+#define read_c0_errctl(x) read_c0_ecc(x)
+#define write_c0_errctl(x) write_c0_ecc(x)
+
+/*
+ * Different semantics to the set_c0_* function built by __BUILD_SET_C0
+ */
+static __cpuinit unsigned int bis_c0_errctl(unsigned int set)
+{
+        unsigned int res;
+        res = read_c0_errctl();
+        write_c0_errctl(res | set);
+        return res;
+}
+
+static __cpuinit void ispram_store_tag(unsigned int offset, unsigned int data)
+{
+        unsigned int errctl;
+
+        /* enable SPRAM tag access */
+        errctl = bis_c0_errctl(ERRCTL_SPRAM);
+        ehb();
+
+        write_c0_taglo(data);
+        ehb();
+
+        cache_op(Index_Store_Tag_I, CKSEG0|offset);
+        ehb();
+
+        write_c0_errctl(errctl);
+        ehb();
+}
+
+
+static __cpuinit unsigned int ispram_load_tag(unsigned int offset)
+{
+        unsigned int data;
+        unsigned int errctl;
+
+        /* enable SPRAM tag access */
+        errctl = bis_c0_errctl(ERRCTL_SPRAM);
+        ehb();
+        cache_op(Index_Load_Tag_I, CKSEG0 | offset);
+        ehb();
+        data = read_c0_taglo();
+        ehb();
+        write_c0_errctl(errctl);
+        ehb();
+
+        return data;
+}
+
+static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
+{
+        unsigned int errctl;
+
+        /* enable SPRAM tag access */
+        errctl = bis_c0_errctl(ERRCTL_SPRAM);
+        ehb();
+        write_c0_dtaglo(data);
+        ehb();
+        cache_op(Index_Store_Tag_D, CKSEG0 | offset);
+        ehb();
+        write_c0_errctl(errctl);
+        ehb();
+}
+
+
+static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
+{
+        unsigned int data;
+        unsigned int errctl;
+
+        errctl = bis_c0_errctl(ERRCTL_SPRAM);
+        ehb();
+        cache_op(Index_Load_Tag_D, CKSEG0 | offset);
+        ehb();
+        data = read_c0_dtaglo();
+        ehb();
+        write_c0_errctl(errctl);
+        ehb();
+
+        return data;
+}
+
+static __cpuinit void probe_spram(char *type,
+            unsigned int base,
+            unsigned int (*read)(unsigned int),
+            void (*write)(unsigned int, unsigned int))
+{
+        unsigned int firstsize = 0, lastsize = 0;
+        unsigned int firstpa = 0, lastpa = 0, pa = 0;
+        unsigned int offset = 0;
+        unsigned int size, tag0, tag1;
+        unsigned int enabled;
+        int i;
+
+        /*
+         * The limit is arbitrary but avoids the loop running away if
+         * the SPRAM tags are implemented differently
+         */
+
+        for (i = 0; i < 8; i++) {
+                tag0 = read(offset);
+                tag1 = read(offset+SPRAM_TAG_STRIDE);
+                pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
+                         type, i, tag0, tag1);
+
+                size = tag1 & SPRAM_TAG1_SIZE_MASK;
+
+                if (size == 0)
+                        break;
+
+                if (i != 0) {
+                        /* tags may repeat... */
+                        if ((pa == firstpa && size == firstsize) ||
+                            (pa == lastpa && size == lastsize))
+                                break;
+                }
+
+                /* Align base with size */
+                base = (base + size - 1) & ~(size-1);
+
+                /* reprogram the base address base address and enable */
+                tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
+                write(offset, tag0);
+
+                base += size;
+
+                /* reread the tag */
+                tag0 = read(offset);
+                pa = tag0 & SPRAM_TAG0_PA_MASK;
+                enabled = tag0 & SPRAM_TAG0_ENABLE;
+
+                if (i == 0) {
+                        firstpa = pa;
+                        firstsize = size;
+                }
+
+                lastpa = pa;
+                lastsize = size;
+
+                if (strcmp(type, "DSPRAM") == 0) {
+                        unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
+                        unsigned int v;
+#define TDAT    0x5a5aa5a5
+                        vp[0] = TDAT;
+                        vp[1] = ~TDAT;
+
+                        mb();
+
+                        v = vp[0];
+                        if (v != TDAT)
+                                printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
+                                       vp, TDAT, v);
+                        v = vp[1];
+                        if (v != ~TDAT)
+                                printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
+                                       vp+1, ~TDAT, v);
+                }
+
+                pr_info("%s%d: PA=%08x,Size=%08x%s\n",
+                        type, i, pa, size, enabled ? ",enabled" : "");
+                offset += 2 * SPRAM_TAG_STRIDE;
+        }
+}
+
+__cpuinit void spram_config(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+        unsigned int config0;
+
+        switch (c->cputype) {
+        case CPU_24K:
+        case CPU_34K:
+        case CPU_74K:
+                config0 = read_c0_config();
+                /* FIXME: addresses are Malta specific */
+                if (config0 & (1<<24)) {
+                        probe_spram("ISPRAM", 0x1c000000,
+                                    &ispram_load_tag, &ispram_store_tag);
+                }
+                if (config0 & (1<<23))
+                        probe_spram("DSPRAM", 0x1c100000,
+                                    &dspram_load_tag, &dspram_store_tag);
+        }
+}