diff options
Diffstat (limited to 'arch/mips/kernel/unaligned.c')
-rw-r--r-- | arch/mips/kernel/unaligned.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3f24a1d45865..36c5212e0928 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c | |||
@@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
240 | break; | 240 | break; |
241 | 241 | ||
242 | case lwu_op: | 242 | case lwu_op: |
243 | #ifdef CONFIG_MIPS64 | 243 | #ifdef CONFIG_64BIT |
244 | /* | 244 | /* |
245 | * A 32-bit kernel might be running on a 64-bit processor. But | 245 | * A 32-bit kernel might be running on a 64-bit processor. But |
246 | * if we're on a 32-bit processor and an i-cache incoherency | 246 | * if we're on a 32-bit processor and an i-cache incoherency |
@@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
278 | *newvalue = value; | 278 | *newvalue = value; |
279 | *regptr = ®s->regs[insn.i_format.rt]; | 279 | *regptr = ®s->regs[insn.i_format.rt]; |
280 | break; | 280 | break; |
281 | #endif /* CONFIG_MIPS64 */ | 281 | #endif /* CONFIG_64BIT */ |
282 | 282 | ||
283 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | 283 | /* Cannot handle 64-bit instructions in 32-bit kernel */ |
284 | goto sigill; | 284 | goto sigill; |
285 | 285 | ||
286 | case ld_op: | 286 | case ld_op: |
287 | #ifdef CONFIG_MIPS64 | 287 | #ifdef CONFIG_64BIT |
288 | /* | 288 | /* |
289 | * A 32-bit kernel might be running on a 64-bit processor. But | 289 | * A 32-bit kernel might be running on a 64-bit processor. But |
290 | * if we're on a 32-bit processor and an i-cache incoherency | 290 | * if we're on a 32-bit processor and an i-cache incoherency |
@@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
320 | *newvalue = value; | 320 | *newvalue = value; |
321 | *regptr = ®s->regs[insn.i_format.rt]; | 321 | *regptr = ®s->regs[insn.i_format.rt]; |
322 | break; | 322 | break; |
323 | #endif /* CONFIG_MIPS64 */ | 323 | #endif /* CONFIG_64BIT */ |
324 | 324 | ||
325 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | 325 | /* Cannot handle 64-bit instructions in 32-bit kernel */ |
326 | goto sigill; | 326 | goto sigill; |
@@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
392 | break; | 392 | break; |
393 | 393 | ||
394 | case sd_op: | 394 | case sd_op: |
395 | #ifdef CONFIG_MIPS64 | 395 | #ifdef CONFIG_64BIT |
396 | /* | 396 | /* |
397 | * A 32-bit kernel might be running on a 64-bit processor. But | 397 | * A 32-bit kernel might be running on a 64-bit processor. But |
398 | * if we're on a 32-bit processor and an i-cache incoherency | 398 | * if we're on a 32-bit processor and an i-cache incoherency |
@@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
428 | if (res) | 428 | if (res) |
429 | goto fault; | 429 | goto fault; |
430 | break; | 430 | break; |
431 | #endif /* CONFIG_MIPS64 */ | 431 | #endif /* CONFIG_64BIT */ |
432 | 432 | ||
433 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | 433 | /* Cannot handle 64-bit instructions in 32-bit kernel */ |
434 | goto sigill; | 434 | goto sigill; |