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-rw-r--r--arch/mips/kernel/traps.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 77cff1f6d050..cb14db3c5764 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1656,7 +1656,6 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1656 unsigned int cpu = smp_processor_id(); 1656 unsigned int cpu = smp_processor_id();
1657 unsigned int status_set = ST0_CU0; 1657 unsigned int status_set = ST0_CU0;
1658 unsigned int hwrena = cpu_hwrena_impl_bits; 1658 unsigned int hwrena = cpu_hwrena_impl_bits;
1659 unsigned long asid = 0;
1660#ifdef CONFIG_MIPS_MT_SMTC 1659#ifdef CONFIG_MIPS_MT_SMTC
1661 int secondaryTC = 0; 1660 int secondaryTC = 0;
1662 int bootTC = (cpu == 0); 1661 int bootTC = (cpu == 0);
@@ -1740,9 +1739,8 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1740 } 1739 }
1741#endif /* CONFIG_MIPS_MT_SMTC */ 1740#endif /* CONFIG_MIPS_MT_SMTC */
1742 1741
1743 asid = ASID_FIRST_VERSION; 1742 if (!cpu_data[cpu].asid_cache)
1744 cpu_data[cpu].asid_cache = asid; 1743 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1745 TLBMISS_HANDLER_SETUP();
1746 1744
1747 atomic_inc(&init_mm.mm_count); 1745 atomic_inc(&init_mm.mm_count);
1748 current->active_mm = &init_mm; 1746 current->active_mm = &init_mm;