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-rw-r--r--arch/mips/kernel/traps.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e83da174b533..08f1edf355e8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void)
1502 status_set); 1502 status_set);
1503 1503
1504 if (cpu_has_mips_r2) { 1504 if (cpu_has_mips_r2) {
1505 unsigned int enable = 0x0000000f; 1505 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
1506 1506
1507 if (!noulri && cpu_has_userlocal) 1507 if (!noulri && cpu_has_userlocal)
1508 enable |= (1 << 29); 1508 enable |= (1 << 29);
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
1510 write_c0_hwrena(enable); 1510 write_c0_hwrena(enable);
1511 } 1511 }
1512 1512
1513#ifdef CONFIG_CPU_CAVIUM_OCTEON
1514 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
1515#endif
1516
1517#ifdef CONFIG_MIPS_MT_SMTC 1513#ifdef CONFIG_MIPS_MT_SMTC
1518 if (!secondaryTC) { 1514 if (!secondaryTC) {
1519#endif /* CONFIG_MIPS_MT_SMTC */ 1515#endif /* CONFIG_MIPS_MT_SMTC */